Interconnect Structure Using Air-Gap Dummy Features to Tune Capacitance
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Solution Overview
Problem
As semiconductor device dimensions decrease, traditional manufacturing methods face challenges in achieving improved sheet resistance, contact resistance, and capacitance, limiting the performance and functionality of integrated circuits.
Innovation Solution
The semiconductor device structure incorporates a gate-all-around (GAA) transistor design with a self-aligned contact (SAC) layer, a contact etch stop layer (CESL), and an interlayer dielectric (ILD) layer, along with an interconnection structure featuring conductive features and a low-k dielectric material to optimize electrical routing and reduce capacitance through the use of dummy conductive features with air gaps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional manufacturing methods are used, then existing process capabilities are maintained, but sheet resistance, contact resistance, and capacitance cannot be improved
Solution Approach 1:
The contact structure is segmented into multiple layers including a first contact, a second contact over the first contact, and a conductive plug connecting them. This segmentation allows independent optimization of each layer's properties to achieve improved sheet resistance and contact resistance while maintaining manufacturability through established multi-layer fabrication processes.
Solution Approach 2:
The invention transitions from planar contacts to vertically stacked three-dimensional contacts with conductive plugs extending through dielectric layers. This dimensional change enables improved electrical properties by creating multiple contact pathways and reducing current density, while the vertical stacking approach remains compatible with existing semiconductor manufacturing capabilities.
2Productivity
If device dimensions are reduced, then higher density and functionality are achieved, but traditional manufacturing methods become inadequate
Solution Approach 1:
Dielectric layers with embedded conductive plugs are formed in advance before final contact formation. This preliminary action allows precise positioning and dimensional control of conductive elements at smaller scales using established lithography and etching processes, enabling higher device density while maintaining manufacturing precision through a sequence of controlled fabrication steps.
Solution Approach 2:
Different dielectric materials with distinct properties (e.g., first dielectric layer with different characteristics than second dielectric layer) are used in different regions of the contact structure. This local quality approach enables optimization of electrical properties such as capacitance and conductivity in specific areas while maintaining overall device density and compatibility with precision manufacturing processes.
3Reliability
If capacitance is controlled precisely, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
Capacitance is controlled by changing physical parameters such as dielectric layer thickness, dielectric material properties, and contact dimensions rather than adding complex control mechanisms. This approach enables precise capacitance tuning through standard fabrication parameter adjustments, improving device performance while avoiding excessive manufacturing complexity.
Solution Approach 2:
The capacitance control function is segmented across multiple dielectric layers and contact structures rather than requiring a single complex component. Each dielectric layer and contact element contributes to the overall capacitance, allowing precise control through incremental adjustments to individual layers while maintaining manageable structural complexity.
Data Source
AI summary
An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric material and a conductive feature extending through the dielectric material. The conductive feature includes a conductive material and has a first top surface. The structure further includes a dummy conductive feature disposed adjacent the conductive feature in the dielectric material, and the dummy conductive feature has a second top surface substantially co-planar with the first top surface. An air gap is formed in the dummy conductive feature.