Dummy Features for Semiconductor Lithography Printability
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Solution Overview
Problem
Conventional photolithographic techniques face challenges in accurately transferring mask patterns to semiconductor wafers due to optical distortions, leading to defects and unintended electrical paths caused by sub-resolution assist features (SRAFs) that are difficult to control and often result in printing errors and circuit malfunctions.
Innovation Solution
The model-based generation of dummy features in proximity to target features on a mask layout, with evaluation of proximity to metal layers and removal of features within a critical distance, merging of dummy features, and modification of geometry to enhance printability and prevent defects, ensuring consistent printing across various process conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sub-resolution assist features (SRAFs) are added to improve printing fidelity, then imaging quality is improved, but printing errors and unintended electrical paths occur
Solution Approach 1:
The patent applies local quality by making SRAFs non-printing in specific locations through selective removal near metal layers. Instead of uniformly applying SRAFs across the entire design, the method evaluates proximity to metal layers and removes SRAFs within critical distances, thereby maintaining high printing fidelity where needed while preventing harmful printing errors and electrical paths in sensitive areas.
Solution Approach 2:
The patent changes the printing parameter of SRAFs from printing to non-printing based on location. By modifying the printability parameter of SRAFs through selective removal near metal layers, the method maintains imaging quality improvement while eliminating the harmful effect of unintended electrical paths and printing errors in critical regions.
2Manufacturing precision
If aggressive SRAF strategy is used to improve imaging quality, then process window bandwidth is improved, but defect generation increases
Solution Approach 1:
The patent implements local quality by applying different SRAF strategies in different regions. Aggressive SRAF placement is used in areas远离 metal layers where imaging quality is the primary concern, while SRAFs are removed or modified in areas near metal layers where defect generation must be prevented. This spatially differentiated approach maintains high process window bandwidth while reducing defect generation.
Solution Approach 2:
The patent introduces an intermediary evaluation step that assesses the proximity of SRAFs to metal layers. This intermediary mechanism acts as a mediator between the aggressive SRAF strategy and the final pattern, selectively removing SRAFs that would cause defects while preserving those that improve imaging quality, thereby reconciling the contradiction between imaging quality and defect generation.
3Manufacturing precision
If SRAFs are positioned adjacent to feature edges to improve contrast, then printing fidelity is improved, but proximity to metal layers causes unintended electrical paths
Solution Approach 1:
The patent applies local quality by positioning SRAFs adjacent to feature edges in regions远离 metal layers to improve contrast and printing fidelity, while removing SRAFs in regions near metal layers to prevent unintended electrical paths. This location-dependent SRAF placement strategy maintains the beneficial contrast enhancement effect while eliminating the harmful electrical path formation.
Solution Approach 2:
The patent extracts harmful SRAFs from the design by removing those positioned within critical distances of metal layers. This extraction process selectively eliminates the specific SRAFs that would create unintended electrical paths while preserving the SRAFs that contribute to improved printing fidelity in safe regions, thereby resolving the contradiction between contrast improvement and electrical path prevention.
Data Source
AI summary
Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.