Non-Printable Dummy Features for IC Pattern Density Uniformity
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Solution Overview
Problem
Current optical proximity correction (OPC) methods in integrated circuit (IC) manufacturing have limited freedom and effectiveness in tuning pattern density and exhibit poor uniformity, leading to issues like dynamic space charge and micro-loading effects during electron-beam lithography, and are time-consuming and costly due to extensive simulations for dummy feature insertion.
Innovation Solution
A method for fabricating ICs that involves generating dummy features with optimized circuit performance by determining a target block dummy density ratio, selecting non-printable dummy features with specific size and pitch to ensure maximum intensity is below the exposure threshold, and adding these features to the IC design layout to improve pattern density uniformity and reduce space charge effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing OPC methods add dummy features to improve imaging resolution, then pattern density can be adjusted, but the degree of freedom and effectiveness are limited and uniformity is poor
Solution Approach 1:
The patent segments the dummy feature insertion process into multiple stages: initial dummy feature addition, classification of space blocks based on pattern density, and subsequent targeted insertion of additional dummy features in low-density regions. This segmented approach provides greater adaptability and effectiveness in tuning pattern density compared to traditional single-stage OPC methods.
Solution Approach 2:
The patent applies local quality by classifying different space blocks into categories (first, second, and third space blocks) based on their pattern density characteristics, and then applying different dummy feature insertion strategies to each class. This localized approach improves both the effectiveness and uniformity of pattern density adjustment across different regions of the IC pattern.
2Manufacturing precision
If dummy features are inserted to improve pattern density uniformity, then imaging quality improves, but extensive simulations and calculations increase time and cost
Solution Approach 1:
The patent performs preliminary classification of space blocks into different categories based on pattern density before the main dummy feature insertion process. By pre-identifying first, second, and third space blocks with different density characteristics, the method reduces the complexity of subsequent simulations and calculations, thereby reducing time and cost while maintaining pattern density uniformity.
Solution Approach 2:
The patent changes the parameter of dummy feature density by inserting different quantities of dummy features into different classes of space blocks. First space blocks receive a first density of dummy features, second space blocks receive a second density, and third space blocks receive a third density. This parameter variation approach achieves pattern density uniformity without requiring extensive simulations for each individual region.
3Device complexity
If traditional OPC methods are used, then process simplicity is maintained, but dynamic space charge effect and micro-loading effect occur during electron-beam lithography
Solution Approach 1:
The patent applies local quality by identifying and separately treating different types of space blocks (first, second, and third space blocks) with different pattern density characteristics. By inserting dummy features selectively into low-density regions (second and third space blocks) with controlled densities, the method addresses micro-loading effects and dynamic space charge effects in electron-beam lithography without significantly increasing overall process complexity.
Data Source
AI summary
The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.