Dummy Features in Redistribution Layers for Fan-Out Packaging
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Solution Overview
Problem
Current wafer level packaging technologies face challenges in efficiently redistributing and connecting input/output pads on semiconductor dies to external connectors, limiting the packaging density and reliability of fan-out packages.
Innovation Solution
The process involves forming integrated fan-out packages with multiple layers of metallization patterns and dielectric layers, including the use of seed layers, conductive materials, and patterning techniques to create redistribution structures that connect integrated circuit dies to external connectors through a series of dielectric and metallization layers, with dummy patterns to improve planarity and reduce stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple layers of metallization patterns and dielectric layers are formed to redistribute I/O pads, then packaging density and connection efficiency are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The redistribution layer structure is divided into multiple separate metallization patterns (first, second, third metallization patterns) stacked at different heights, with each layer performing specific routing functions. This segmentation allows complex I/O redistribution to be achieved through modular layers, improving packaging density while managing complexity through systematic layering.
Solution Approach 2:
The patent utilizes vertical stacking of metallization patterns at different heights (first height, second height, third height) to achieve three-dimensional I/O redistribution. By adding the vertical dimension, the design redistributes I/O pads in multiple layers rather than relying solely on planar expansion, thereby increasing packaging density without proportionally increasing manufacturing complexity.
2Reliability
If dummy patterns are added to improve planarity and reduce stress, then manufacturing reliability is improved, but device complexity increases
Solution Approach 1:
Dummy patterns are strategically positioned between the first and second metallization patterns, and between the second and third metallization patterns, to provide stress relief and planarity compensation before manufacturing defects can occur. These dummy structures act as preventive measures, cushioning against potential manufacturing failures by compensating for stress accumulation and surface irregularities in advance.
Solution Approach 2:
The dummy patterns are selectively placed in specific locations where stress concentration or planarity issues are anticipated, rather than uniformly distributing them across the entire structure. This localized approach improves reliability at critical points while minimizing the overall increase in device complexity.
3Reliability
If conductor posts and vias are formed to electrically connect metallization patterns, then electrical connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Conductor posts are formed in advance within the dielectric material to establish vertical electrical pathways before the metallization patterns are deposited. This preliminary formation of conductive vias ensures that subsequent metallization layers can be aligned to predetermined connection points, reducing the alignment precision requirements during later manufacturing steps and improving overall electrical connectivity reliability.
Data Source
AI summary
An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.


