Dummy Fin Gap Filling With High-k and Flowable Oxide Layers
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Solution Overview
Problem
The semiconductor industry faces challenges in gap filling between high aspect ratio semiconductor fins due to fin-to-fin bending and the formation of seams and voids caused by single ALD high-k films, which can degrade AC performance and lead to RC delay.
Innovation Solution
A bi-layer approach using atomic layer deposition (ALD) of a high-k dielectric layer and a flowable oxide layer is employed to form a dummy fin, reducing intermolecular forces and preventing fin-to-fin bending, while maintaining better shape profile control and lower k-value to preserve AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single ALD high-k film is used to fill gaps between fins, then gap filling is achieved, but fin-to-fin bending and seams/voids occur
Solution Approach 1:
The patent divides the single high-k film deposition into multiple sequential ALD cycles with intermediate etch steps. The process segments the gap filling into stages: initial high-k layer deposition, selective etching of excess material, additional high-k layer deposition, and final planarization. This segmentation prevents the intermolecular forces from causing fin bending while achieving complete gap filling.
Solution Approach 2:
The patent applies preliminary etching steps before completing the high-k film deposition. By performing selective etching of the high-k material between deposition cycles, the process prevents the accumulation of excessive intermolecular forces that would cause fin bending, while still allowing subsequent layers to fill the gaps effectively.
2Reliability
If high-k dielectric material is deposited to fill gaps, then AC performance may be improved, but RC delay increases due to higher dielectric constant
Solution Approach 1:
The patent changes the dielectric constant parameter by using a composite structure: a first high-k dielectric layer with higher k-value for AC performance, and a second low-k dielectric layer with lower k-value to reduce RC delay. This parameter optimization allows the structure to achieve both improved AC performance and reduced signal delay.
Solution Approach 2:
The patent employs a composite dielectric structure combining high-k and low-k materials. The first high-k dielectric layer provides the necessary electrical performance, while the second low-k dielectric layer reduces the overall capacitance and RC delay. This composite approach allows simultaneous optimization of conflicting electrical characteristics.
3Device complexity
If single ALD high-k film is used, then process simplicity is maintained, but seams and voids form in the dummy fin
Solution Approach 1:
The patent segments the deposition process into multiple ALD cycles with intermediate etching and planarization steps. Each deposition-etch cycle fills gaps further while removing defective material, ensuring uniform dummy fin formation without seams or voids.
Solution Approach 2:
The process incorporates feedback through selective etching steps that remove excess or defective high-k material between deposition cycles. This feedback mechanism ensures that only properly formed material remains, eliminating seams and voids while maintaining process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the formation of seams and voids, prevents fin-to-fin bending, and lowers the dielectric constant of the dummy fin, thereby enhancing AC performance and reducing RC delay.
Implementation Method 1
forming a first high-k layer conformally over the dielectric layer by introducing a bi-layer approach using an atomic layer deposition (ALD) of a high-k dielectric layer
Implementation Method 2
a flowable oxide layer deposition. This bi-layer dummy fin formation procedure can overcome a potential fin to fin bending effect from the high-k layer
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.