Dummy Fin Gate Isolation Layout to Prevent FinFET Gate Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The poly depletion effect in MOS devices with polysilicon gate electrodes increases the effective gate dielectric thickness, making it difficult to create an inversion layer at the semiconductor surface, which is addressed by forming metal gate electrodes with appropriate work functions, but the process of forming metal gates involves complex steps including dummy gate dielectric removal and CMP processes.
Innovation Solution
The selective removal of dummy gate dielectrics from dielectric dummy fins before forming gate isolation regions simplifies the process flow and prevents leakage by ensuring that gate isolation regions physically contact the dummy fin without leaving spaces that could be filled with replacement gate electrodes, thus eliminating the risk of leakage between gate stacks and dummy fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy gate dielectrics are not removed from dummy fins before forming gate isolation regions, then spaces remain that could be filled with replacement gate electrodes, but the process becomes more complex and leakage risk increases
Solution Approach 1:
The dummy gate dielectric is removed from the dummy fin before the gate isolation region is formed. This preliminary removal action ensures that when the gate isolation region is subsequently deposited, it directly contacts the dummy fin surface without any intervening spaces that could be filled with replacement gate electrode material, thereby preventing leakage while simplifying the overall process
2Manufacturing precision
If gate isolation regions are formed before removing dummy gate dielectrics, then spaces may be created between gate isolation regions and dummy fins, but this requires additional process steps
Solution Approach 1:
The removal of the dummy gate dielectric is performed as a preliminary step before forming the gate isolation region. This sequencing ensures that the gate isolation region is deposited directly onto the exposed dummy fin surface, achieving precise contact and eliminating spaces that would require additional process steps to correct, thereby improving both manufacturing precision and productivity
Data Source
AI summary
A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.