Dummy Fin Profile Shaping for Wider FinFET Gate Patterning Window
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Solution Overview
Problem
The poly depletion effect in MOS devices with polysilicon gate electrodes increases the effective gate dielectric thickness, making it difficult to create an inversion layer, which is addressed by forming metal or metal silicide gate electrodes, but these have different work function requirements for NMOS and PMOS devices, complicating the process.
Innovation Solution
The formation of dummy fins with reduced top width, achieved through etching, simplifies the patterning process for dummy and replacement gate stacks, thereby enlarging the process window by reducing the aspect ratio of trenches and facilitating easier patterning and deposition of layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy fins with standard top width are used, then the gate stack formation is more straightforward, but the aspect ratio of trenches becomes high making patterning difficult
Solution Approach 1:
The dummy fin structure is made asymmetric with a reduced top width compared to the bottom width, creating a tapered profile. This asymmetric geometry reduces the aspect ratio of trenches formed during gate stack patterning, making the patterning process easier while maintaining the dummy fin's functional role in defining gate alignment.
Solution Approach 2:
The top width parameter of the dummy fin is specifically reduced to optimize the aspect ratio of subsequent trenches. By changing this geometric parameter, the patterning process becomes more feasible without compromising the overall device performance or gate alignment accuracy.
2Reliability
If metal or metal silicide gate electrodes are formed to solve poly depletion effect, then the inversion layer formation is improved, but different work function requirements for NMOS and PMOS devices complicate the process
Solution Approach 1:
The dummy fin structure serves multiple functions: it defines gate alignment, controls trench aspect ratio, and enables universal processing for both NMOS and PMOS devices. By using the same dummy fin-based approach for both device types, the methodology provides a universal solution that avoids the complexity of different work function requirements for metal gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the difficulty in forming gate stacks and enlarges the process window, making it easier to pattern and deposit layers, thus improving the fabrication of FinFETs by reducing the top width of dummy fins and enhancing the formation of gate isolation regions.
Implementation Method 1
etching the dielectric dummy fin more than a bottom width of the dielectric dummy fin
Data Source
AI summary
A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.