Dummy Fin Core-Shell Structure for Leakage Isolation in FinFETs
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Solution Overview
Problem
Dummy fins in semiconductor devices can form voids that lead to leakage paths, reducing electrical isolation and device performance, and may suffer from bending issues causing AC performance degradation.
Innovation Solution
A dummy fin configuration with a low-k dielectric constant outer shell and a high-k dielectric constant inner core is used to fill voids, preventing leakage paths and enhancing electrical isolation, while being compatible with finFET formation processes to minimize processing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy fins are formed in semiconductor devices, then electrical isolation between active fins is improved, but voids form in the dummy fins creating leakage paths that reduce isolation performance
Solution Approach 1:
The patent changes the material parameter of the dummy fin from conventional materials to materials with negative Poisson's ratio (auxetic materials). This parameter change causes the material to expand in the lateral direction when compressed vertically during fabrication, automatically filling voids and preventing leakage paths while maintaining electrical isolation functionality
Solution Approach 2:
The patent employs composite material structures where auxetic materials are combined with conventional semiconductor materials. The auxetic material core provides void-filling and leakage prevention, while the surrounding conventional materials maintain structural integrity and electrical isolation, creating a composite dummy fin that resolves both isolation and void formation issues
2Reliability
If dummy fins are used for electrical isolation, then device performance is improved, but bending issues in dummy fins cause AC performance degradation
Solution Approach 1:
The patent modifies the mechanical parameter of the dummy fin by using materials with negative Poisson's ratio. These auxetic materials exhibit enhanced shear modulus and resistance to bending deformations, maintaining structural stability and preventing AC performance degradation while preserving the electrical isolation function
Solution Approach 2:
The patent designs the dummy fin with a core-shell structure where the auxetic material core provides mechanical stability against bending, while the outer shell maintains electrical isolation. This differentiated design allows each layer to perform its specific function optimally, preventing both bending issues and maintaining device performance
3Ease of manufacture
If conventional dummy fin structures are formed, then manufacturing process is simplified, but leakage paths reduce electrical isolation effectiveness
Solution Approach 1:
The patent introduces a parameter change in the material properties (negative Poisson's ratio) that enables the dummy fin to self-fill voids during standard fabrication processes. This material parameter change maintains ease of manufacture while automatically preventing leakage paths, as the auxetic expansion occurs naturally during compression steps in existing manufacturing flows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the electrical isolation and performance of semiconductor devices by blocking leakage paths and avoiding AC performance degradation, while being easily integrated into existing finFET processes.
Implementation Method 1
A dummy fin configuration with a low-k dielectric constant outer shell and a high-k dielectric constant inner core is used to fill voids, preventing leakage paths and enhancing electrical isolation
Data Source
AI summary
A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.