Dummy Fin Profile Control for FinFET Gate Process Window
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Solution Overview
Problem
Metal-Oxide-Semiconductor (MOS) devices with polysilicon gate electrodes face a carrier depletion effect, known as poly depletion, which increases the effective gate dielectric thickness and makes it difficult to create an inversion layer, limiting the performance of Fin Field-Effect Transistors (FinFETs).
Innovation Solution
The formation of dummy fins with a reduced top width, achieved through etching, facilitates easier patterning and formation of replacement gate stacks, thereby enlarging the process windows and improving the formation of FinFETs by reducing the aspect ratio of trenches and making the patterning process more manageable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy fins with standard top width are used, then the gate stack formation is more straightforward, but the aspect ratio of trenches becomes high making patterning difficult and process window narrow
Solution Approach 1:
The dummy fin is designed with an asymmetric cross-sectional profile where the top width is reduced relative to the bottom width. This asymmetric geometry reduces the aspect ratio of the trench formed during gate stack fabrication, making the patterning process easier and enlarging the process window while maintaining the dummy fin's function in preventing poly depletion.
Solution Approach 2:
The top width parameter of the dummy fin is specifically reduced compared to conventional dummy fins with uniform width. This parameter change in the dummy fin geometry directly addresses the high aspect ratio problem in trench formation, enabling better patterning control without sacrificing the electrical performance benefits.
2Reliability
If polysilicon gate electrodes are used, then the work function can be adjusted to band-edge, but carrier depletion effect increases effective gate dielectric thickness
Solution Approach 1:
A dummy fin structure is introduced as an intermediary element between the source/drain regions and the gate stack. This dummy fin acts as a mediator that prevents carrier depletion at the gate dielectric interface by providing a physical barrier that blocks the depletion region extension, thereby maintaining effective gate control without requiring material substitution.
Solution Approach 2:
The dummy fin is formed as a simplified copy or replica of the actual fin structure, using the same semiconductor material and basic geometry but without the need for complex metal gate stacking. This copied structure suffices to prevent poly depletion while the actual gate stack can be optimized separately for performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of FinFETs by reducing the top width of dummy fins, making it easier to pattern and form replacement gate stacks, thus enhancing the overall process efficiency and device performance by reducing the poly depletion effect.
Implementation Method 1
etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin
Data Source
AI summary
A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.