Reduced-Height Dummy Fin Layout for Larger FinFET Source/Drain Regions
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Solution Overview
Problem
The poly depletion effect in MOS devices with polysilicon gate electrodes increases the effective gate dielectric thickness, making it difficult to create an inversion layer at the semiconductor surface, which can be mitigated by forming metal gate electrodes but requires complex processes involving dummy gate dielectrics and electrodes.
Innovation Solution
The formation of Fin Field-Effect Transistors (FinFETs) with source/drain regions separated by partially recessed and narrowed dummy fins, allowing for the reduction of dummy fin height and width, which creates additional space for source/drain regions and improves transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal gate electrodes are formed to solve the poly depletion effect, then the inversion layer creation is improved, but the device complexity increases due to the need for dummy gate dielectrics and electrodes
Solution Approach 1:
The patent removes the dummy gate dielectric and dummy gate electrode structures that were previously necessary to define the gate region. By using recessed source/drain regions that directly expose the semiconductor fin, the gate electrode can be formed without requiring these additional dummy structures, thereby simplifying the overall device architecture while maintaining the ability to create inversion layers.
Solution Approach 2:
The recessed source/drain region structure serves multiple functions: it defines the gate region, enables proper gate electrode formation, and eliminates the need for separate dummy gate structures. This multi-functional approach reduces device complexity while maintaining the electrical performance needed for inversion layer creation.
2Volume of moving object
If dummy fins are fully removed to increase source/drain volume, then the source/drain region volume is improved, but the electrical short likelihood increases
Solution Approach 1:
The patent applies different treatments to different portions of the dummy fin structure. The dummy fin is recessed in the source/drain region to increase volume, but the gate region portion is maintained at the original height. This local differentiation allows the source/drain regions to expand and improve volume while the gate region maintains proper electrical isolation, preventing shorts.
Solution Approach 2:
The dummy fin structure is segmented into different height portions: a first portion in the source/drain region that is recessed to increase volume, and a second portion in the gate region that maintains the original height to prevent electrical shorts. This segmentation allows simultaneous optimization of both volume and electrical isolation.
3Area of stationary object
If dummy fin height is reduced to create additional space, then the source/drain region space is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs the dummy fin recess operation before gate electrode formation. By pre-recessing the dummy fin in the source/drain region while maintaining the gate region height, the structure is prepared in advance for subsequent gate formation. This preliminary action simplifies later manufacturing steps and reduces the precision requirements for subsequent processes.
Solution Approach 2:
The recess operation is applied locally only to portions of the dummy fin in the source/drain regions, while the gate region portions maintain their original height. This selective local modification creates the necessary space for source/drain regions without requiring high-precision control across the entire structure, as only specific areas are modified.
Data Source
AI summary
A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.