Dummy Gate Alignment Structure Without Footing Features
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, the integration of smaller features leads to challenges in aligning active gate structures with source/drain contacts, resulting in reduced yield and reliability of FinFET devices due to the formation of footing features at the edges of dummy gates during the manufacturing process.
Innovation Solution
The formation of an alignment structure comprising dummy gates without footing features, which prevents the formation of these unwanted features and improves the alignment between active gate structures and source/drain contacts, enhancing the yield and reliability of FinFET devices by using specific etch processes and reshaping techniques to create notches in the sacrificial gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates are formed during the manufacturing process to assist alignment, then alignment between active gate structures and source/drain contacts is improved, but footing features form at the edges of dummy gates causing shorting and reducing yield
Solution Approach 1:
The patent removes the harmful footing features from the dummy gate edges through selective etching processes. By extracting only the problematic portions at the edges while preserving the main dummy gate structure, the alignment function is maintained while the shorting issue is eliminated.
Solution Approach 2:
The patent applies different treatments to different parts of the dummy gates: the edges are selectively modified to remove footing features while the central portions retain their original structure. This local differentiation allows the dummy gates to provide alignment guidance without creating harmful shorting paths.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but alignment challenges and footing feature formation increase
Solution Approach 1:
The patent performs preliminary reshaping of the dummy gates before the main alignment and patterning steps. By pre-modifying the dummy gate edges to prevent footing feature formation, subsequent processing steps can proceed without alignment errors or shorting issues, enabling reliable miniaturization.
Data Source
AI summary
An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region.