Dummy Gate Backside Power Connections Without uTSV KOZ Penalty
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Solution Overview
Problem
As micro-through silicon via (uTSV) diameter increases, the keep-out-zone (KOZ) also increases, posing challenges in chip area usage and fabrication complexity for back-side power distribution networks (PDN) connections.
Innovation Solution
The method involves forming sacrificial contact plugs and fill regions, replacing dummy gate structures, and inverting the substrate to create self-aligned backside power connections, reducing the need for independent through silicon vias (TSVs) and minimizing chip area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If micro-through silicon via (uTSV) diameter increases, then the keep-out-zone (KOZ) area increases, but chip area usage efficiency deteriorates
Solution Approach 1:
The patent merges the power delivery network connections with dummy gate structures. The dummy gates, which are non-functional structures used for process control, are repurposed to provide electrical connections for power delivery. This integration eliminates the need for separate TSV structures and their associated keep-out zones, thereby improving chip area usage while maintaining manufacturing precision.
Solution Approach 2:
The dummy gate structures serve multiple functions: they act as process control elements during fabrication and simultaneously serve as power delivery network connections. This multi-functionality reduces the need for dedicated power connection structures, minimizing the keep-out-zone area and improving overall chip area efficiency.
2Manufacturing precision
If micro-through silicon via (uTSV) diameter increases, then the keep-out-zone (KOZ) area increases, but fabrication complexity increases
Solution Approach 1:
The patent combines power delivery network formation with existing dummy gate fabrication processes. By integrating these functions, the number of separate fabrication steps is reduced, simplifying the overall manufacturing process while maintaining the precision required for uTSV diameter control.
Solution Approach 2:
The dummy gate structures are formed during earlier fabrication stages as part of the standard process flow. By preparing these structures in advance, the patent eliminates the need for additional later-stage processing steps, thereby reducing fabrication complexity while maintaining manufacturing precision.
3Area of stationary object
If dummy gate structures are used for backside power connections, then chip area usage improves, but process complexity increases
Solution Approach 1:
The dummy gate structures perform dual roles: serving as process control elements during fabrication and as power delivery network connections. This multi-functionality maximizes chip area usage by eliminating dedicated power connection structures, while the process complexity is managed by integrating these functions into existing fabrication workflows rather than adding separate processes.
Data Source
AI summary
A method of forming a backside power connection is provided. The method includes forming a plurality of sacrificial contact plugs and a plurality of sacrificial fill regions on a substrate, and forming a source/drain over a first sacrificial contact plug. The method further includes forming a replacement metal gate structure over a first sacrificial fill region, and forming an electrical contact to each of the replacement metal gate structure and the source/drain. The method further includes inverting the plurality of sacrificial contact plugs, source/drain, replacement metal gate structure, and substrate. The method further includes removing the first sacrificial contact plug and the first sacrificial fill region, and forming a first conductive contact to the source/drain and a second conductive contact to the replacement metal gate structure.