Dummy Gate Cell Antenna Effect Suppression
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Solution Overview
Problem
As integrated circuits (ICs) shrink in size, the antenna effect becomes more pronounced, leading to degradation of device characteristics due to charge accumulation and flow through gate electrodes, and existing countermeasures to reduce wiring length and increase antenna diode area compromise wiring convenience and area usage efficiency.
Innovation Solution
A dummy gate cell is introduced, comprising an nMOS and a pMOS transistor with disconnected drain electrodes, placed in unused areas of a cell-based IC, connected to external wiring to suppress the antenna effect without affecting power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the length of wiring directly connected to gate electrode is restrained to reduce antenna ratio, then antenna effect is suppressed, but wiring convenience is lowered
Solution Approach 1:
The patent introduces a dummy gate cell as an intermediary element between the signal wiring and the actual gate electrode. This dummy gate cell includes a gate electrode connected to the signal wiring, but its drain electrodes are not connected to form a complete circuit. The dummy gate cell acts as a mediator that provides a safe path for charge dissipation without creating a direct conductive path that would compromise wiring convenience or create functional antenna effects.
2Object-affected harmful factors
If the area of antenna diode is increased to increase maximum ratio, then antenna effect is suppressed, but area usage efficiency is degraded
Solution Approach 1:
The patent creates a simplified copy or replica of a gate cell structure - the dummy gate cell - that mimics the essential geometry and connectivity of a functional gate cell without replicating its full functionality. The dummy gate cell has the same gate electrode, source, and drain structures, but with disconnected drain electrodes that prevent current flow. This copying approach provides the charge dissipation function of larger antenna diodes while occupying minimal area, thus maintaining area usage efficiency.
3Productivity
If IC size is reduced, then integration density is improved, but antenna effect is enhanced due to charge accumulation
Solution Approach 1:
The patent segments the gate cell structure into functional and non-functional components. The dummy gate cell represents a segmented version where the gate electrode and source are present but the drain connection is intentionally separated or disconnected. This segmentation allows the dummy gate cell to be distributed throughout the IC layout in unused areas, providing localized charge dissipation points that scale with integration density without requiring proportional increases in antenna diode area or compromising wiring flexibility.
Data Source
AI summary
A dummy gate cell includes an nMOS transistor and a pMOS transistor, wherein a drain electrode of the nMOS transistor is not connected to a drain electrode of the pMOS transistor and the dummy gate cell is disposed in an unused area not occupied by a basic cell in a cell-based IC.