Dummy Gate Dielectric Layout for Uniform Nanosheet Channel Thickness
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Solution Overview
Problem
Existing semiconductor manufacturing technologies face challenges during the removal of buffer layers in non-planar transistor devices, as the etching process can inadvertently damage the topmost channel layer, leading to uneven channel layer thicknesses and increased fabrication complexity.
Innovation Solution
The proposed method skips the deposition of the buffer layer, allowing for the direct formation of a dummy gate dielectric layer on the topmost channel layer, which eliminates the need for a buffer layer etching step, thereby maintaining the integrity of the channel layers and reducing manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a buffer layer is deposited before the dummy gate dielectric layer, then the dummy gate dielectric layer can be formed, but the buffer layer etching process can inadvertently damage the topmost channel layer, leading to uneven channel layer thicknesses
Solution Approach 1:
The patent removes the buffer layer from the structure entirely, eliminating the need for buffer layer etching. By depositing the dummy gate dielectric layer directly on the topmost channel layer without an intervening buffer layer, the harmful etching process that could damage the channel layer is completely avoided, thereby maintaining channel layer thickness uniformity.
Solution Approach 2:
The patent segments the manufacturing process by eliminating the buffer layer deposition step, thereby simplifying the structure to consist of only the essential layers (channel layer and dummy gate dielectric layer). This segmentation removes the source of potential damage while preserving the functional integrity of the device.
2Ease of manufacture
If a buffer layer is deposited and subsequently etched, then the dummy gate dielectric layer formation is enabled, but the fabrication process complexity increases due to additional etching steps
Solution Approach 1:
The patent extracts and removes the buffer layer from the fabrication sequence, eliminating the associated etching step. This reduction in process steps simplifies the overall fabrication process while still enabling successful formation of the dummy gate dielectric layer directly on the channel layer.
Solution Approach 2:
By segmenting out the buffer layer deposition and etching steps from the fabrication process, the patent creates a more streamlined manufacturing sequence that focuses only on the essential layers, thereby reducing process complexity without compromising the ability to form the dummy gate dielectric layer.
3Ease of manufacture
If additional etching steps are performed to remove the buffer layer, then the dummy gate structure can be formed, but manufacturing costs increase
Solution Approach 1:
The patent extracts the buffer layer removal step from the manufacturing process by not depositing the buffer layer in the first place. This eliminates the time and cost associated with buffer layer etching while still achieving the necessary dummy gate structure formation.
Solution Approach 2:
By segmenting the fabrication process to exclude buffer layer deposition and etching, the patent reduces the total number of manufacturing steps, thereby decreasing both fabrication time and associated costs while maintaining the ability to form the dummy gate structure.
Data Source
AI summary
A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.