Dummy Gate Thickness Uniformity via CMP Mask Patterns
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Solution Overview
Problem
The traditional FinFET process faces challenges in forming dummy gates with uniform thickness due to the loading effect during chemical mechanical polishing (CMP), leading to thickness variations and performance issues in semiconductor devices.
Innovation Solution
The method involves forming mask patterns in non-target areas before CMP, which act as a polishing stop layer to ensure even thickness of target patterns, such as dummy gates, by using a hard mask layer and controlling polishing selectivity ratios, thereby avoiding the CMP loading effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMP is performed on dummy gate layer without mask patterns, then CMP process can be completed, but thickness variation of dummy gate layer becomes large due to loading effect
Solution Approach 1:
Mask patterns are formed in non-target areas before the CMP process to prevent the loading effect from occurring during polishing. This preliminary action ensures that the dummy gate layer is polished to a uniform thickness without the adverse effects of the loading effect.
Solution Approach 2:
Mask patterns serve as an intermediary element during the CMP process. These mask patterns are placed in non-target areas to modify the polishing behavior, allowing the dummy gate layer to be polished uniformly without direct contact between the polishing pad and the dummy gate structures in non-target areas.
2Manufacturing precision
If dummy gate layer thickness is made uniform using mask patterns, then target pattern thickness uniformity is improved, but process complexity increases due to additional mask formation and removal steps
Solution Approach 1:
Mask patterns are selectively formed only in non-target areas where they are needed to control the polishing process. The mask patterns are not formed in target areas, allowing the dummy gate layer to be formed with the desired pattern and thickness in those regions. This local application of mask patterns minimizes the impact on overall process complexity.
Solution Approach 2:
The mask patterns are temporary structures that are formed, used during CMP, and then removed. After serving their purpose of controlling the polishing process to achieve uniform thickness, the mask patterns are discarded through removal steps, leaving only the uniformly thick dummy gate layer in the target areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of target patterns with substantially equal thickness, reducing defects like dummy gate residues and gate trench widening, thereby enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
a chemical mechanical polishing (CMP) step is performed to make the dummy gate layer flat
Data Source
AI summary
A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.