High Aspect Ratio Dummy Gate Collapse Prevention
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Solution Overview
Problem
In semiconductor manufacturing, high aspect ratio dummy gates in shallow trench isolation regions are prone to collapse, leading to defects and yield issues due to their instability, which complicates the fabrication of transistors with reduced gate length for advanced CMOS scaling.
Innovation Solution
The method involves forming narrow active gates around fins and wide dummy gates above isolation regions using different hardmask materials, such as amorphous silicon germanium and amorphous silicon, to reduce the aspect ratio of dummy gates, preventing collapse and allowing for tighter contact gate pitch without mechanical instability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If dummy gates are made narrow to reduce gate length for CMOS scaling, then transistor pitch is reduced, but dummy gates in isolation regions collapse due to high aspect ratio
Solution Approach 1:
The patent applies different hardmask materials to different regions: amorphous silicon germanium (a-SiGe) in active regions and amorphous silicon (a-Si) in isolation regions. This local differentiation allows narrow gates in active regions while creating wider, more stable dummy gates in isolation regions, resolving the contradiction between gate length reduction and dummy gate stability.
Solution Approach 2:
The patent changes the material parameter (hardmask material composition) between regions to achieve different etch rates. The a-SiGe hardmask has greater lateral etch than a-Si hardmask, resulting in different final gate widths from the same initial pattern, thereby enabling narrow active gates and wide stable dummy gates simultaneously.
2Reliability
If dummy gates are made wide to prevent collapse, then mechanical stability is improved, but contact gate pitch increases reducing productivity
Solution Approach 1:
The patent creates different gate widths in different regions by using region-specific hardmask materials. Isolation region dummy gates are made wide for stability, while active region gates remain narrow for tight pitch, thus resolving the contradiction between stability and productivity.
Solution Approach 2:
The patent segments the hardmask layer into different materials for different regions, allowing independent optimization of gate width in isolation regions versus active regions. This segmentation enables wide dummy gates without increasing overall device pitch.
3Ease of manufacture
If uniform hardmask material is used, then fabrication process is simplified, but cannot achieve different gate widths for active and isolation regions
Solution Approach 1:
The patent uses different hardmask materials in different regions to achieve local optimization: a-SiGe for narrow active gates and a-Si for wide dummy gates. This local quality approach enables gate width differentiation while maintaining a relatively simple sequential deposition process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of transistors with small gate length without dummy gate collapse, improving mechanical stability and reducing waste by allowing wider dummy gates in isolation regions, thus enhancing the reliability of transistor devices.
Implementation Method 1
the first hardmask material having a greater lateral etch than the second hardmask material
Data Source
AI summary
A method for fabricating transistors comprises forming a fin above a semiconductor substrate; forming an isolation region with a dielectric material, the top surface of the isolation dielectric below the top of fin surface; depositing a dummy gate layer above the isolation region and surrounding the fin, a dummy gate hardmask layer on top of the dummy gate layer, a first hardmask material on top of the dummy gate hardmask layer above the fin and a second hardmask material on top of the dummy gate hardmask layer above the isolation region, the first hardmask material having a greater lateral etch than the second hardmask material; applying a gate patterning mask spaced equidistantly apart on top of the first and second hardmask materials; and etching the transistor to simultaneously form narrow active gates above and surrounding the fin and wide dummy gates above the isolation region.