Dummy Gate Critical Dimension Control in Gate-Last Process
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Solution Overview
Problem
In the gate-last process for manufacturing MOSFETs, the critical dimension and profile of the dummy gate cannot be accurately controlled at the 22 nm node and beyond, leading to degraded gate Line Edge Roughness (LER), device performance, and reliability.
Innovation Solution
A method involving the deposition of a gate oxide layer, bottom-layer amorphous silicon, an oxide-nitride-oxide structured hard mask, and a top-layer amorphous silicon, followed by precise etching and trimming of photoresist lines to ensure the dummy gate's critical dimension and profile are accurately controlled, utilizing specific deposition techniques like LPCVD, PECVD, and APCVD, and etching methods such as RIE.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dummy gate manufacturing methods are used in gate-last process, then the manufacturing process can be completed, but the critical dimension and profile of the dummy gate cannot be accurately controlled at 22 nm node and beyond
Solution Approach 1:
The dummy gate structure is divided into multiple layers: gate oxide layer, bottom-layer amorphous silicon, ONO structured hard mask, and top-layer amorphous silicon. This segmentation allows each layer to be precisely controlled during deposition, enabling accurate critical dimension control at 22 nm node and beyond while reducing gate LER
Solution Approach 2:
The method performs preliminary deposition of multiple layers with specific thicknesses before the final etching step. The gate oxide layer (50-100 nm), bottom-layer amorphous silicon (200-500 nm), ONO hard mask (100-200 nm), and top-layer amorphous silicon (200-500 nm) are deposited in advance with precise thickness control, ensuring that the subsequent etching process can accurately define the dummy gate profile and critical dimension
2Manufacturing precision
If conventional dummy gate manufacturing methods are used in gate-last process, then the manufacturing process can be completed, but the profile of the dummy gate cannot be accurately controlled
Solution Approach 1:
The dummy gate is segmented into distinct functional layers (gate oxide, bottom amorphous silicon, ONO hard mask, top amorphous silicon) that can be independently controlled during deposition. This segmentation enables precise profile control by adjusting the thickness and material properties of each layer, while the systematic multi-step process manages the complexity through organized process sequencing
Solution Approach 2:
The method employs parameter changes in the deposition process, including varying deposition techniques (LPCVD for amorphous silicon, PECVD for oxide layers), controlling deposition temperatures, and adjusting layer thicknesses. These parameter changes enable precise control over the dummy gate profile while the systematic process management handles the complexity of multiple deposition and etching steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively improves the accuracy of the dummy gate's critical dimension and profile, enhancing gate LER, device performance, and reliability at the 22 nm node and beyond.
Implementation Method 1
growing a gate oxide layer on the semiconductor substrate
Implementation Method 2
depositing bottom-layer amorphous silicon (α-Si) on the gate oxide layer
Implementation Method 3
depositing an oxide-nitride-oxide (ONO) structured hard mask on the bottom-layer α-Si
Implementation Method 4
forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines
Implementation Method 5
etching the hard mask layer, the top-layer α-Si, the ONO structured hard mask and the bottom-layer α-Si
Data Source
AI summary
A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.