Dummy Gate Electrode Pattern Density and Decoupling Capacitor
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Solution Overview
Problem
In semiconductor devices of the 90 nm generation or later, there is a significant increase in variation of processing dimensions of gate electrodes and power source noise, making it difficult to achieve high speed and low power consumption, particularly in logic blocks where pattern density is uneven, leading to increased power source noise and erroneous operations.
Innovation Solution
A semiconductor device with a logic block featuring a normal cell region and a vacant region, where a comb-shaped gate electrode is formed in the normal cell region and a comb-shaped dummy gate electrode is formed in the vacant region, connected via wiring to create a decoupling capacitor through electrostatic capacity between the dummy gate electrode and the semiconductor substrate, thereby suppressing variations in processing dimensions and power source noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If miniaturization is pursued in the 90 nm generation or later, then device size is reduced, but variation of processing dimensions of gate electrodes increases
Solution Approach 1:
The patent applies local quality by forming dummy gate electrodes specifically in vacant regions of the logic block, creating non-uniform pattern density distribution. This local modification compensates for processing dimension variations in specific areas without affecting the overall device miniaturization, thereby resolving the contradiction between reduced device size and increased manufacturing precision variation
Solution Approach 2:
The patent changes the pattern density parameter by introducing dummy gate electrodes in vacant regions, transforming the uniform low-density vacant regions into high-density regions. This parameter change compensates for processing dimension variations caused by miniaturization, allowing the device to maintain manufacturing precision while pursuing smaller dimensions
2Device complexity
If pattern density in logic block is uneven, then device complexity is reduced, but power source noise increases
Solution Approach 1:
The patent applies local quality by selectively modifying the vacant regions with dummy gate electrodes, creating local high-density regions that suppress power source noise. This approach maintains the overall simplicity of the logic block design while locally addressing the power source noise issue, thus resolving the contradiction between device complexity and harmful factors
Solution Approach 2:
The patent converts the harmful effect of power source noise into a beneficial outcome by utilizing the vacant regions (which would otherwise be empty space) to form decoupling capacitors. The dummy gate electrodes in these regions serve dual purposes: maintaining pattern density and creating capacitance to suppress power source noise, thereby converting potential harm into benefit
3Object-generated harmful factors
If decoupling capacitor is added to suppress power source noise, then power source noise is reduced, but device area increases
Solution Approach 1:
The patent merges the function of pattern density maintenance with the function of decoupling capacitor formation by using the same dummy gate electrodes in vacant regions for both purposes. This integration eliminates the need for separate decoupling capacitor structures, thereby suppressing power source noise without increasing device area
Solution Approach 2:
The dummy gate electrodes in the vacant regions serve multiple functions: they maintain pattern density uniformity across the logic block and simultaneously form decoupling capacitors to suppress power source noise. This multi-functionality allows the device to reduce power source noise without dedicating additional area solely for noise suppression
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the variation of processing dimensions and power source noise in semiconductor devices, enhancing performance and reliability by unifying pattern density and utilizing the vacant region to integrate a decoupling capacitor, thus improving the stability and efficiency of the semiconductor device.
Implementation Method 1
an electrostatic capacity between at least the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of a power source
Data Source
AI summary
A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.