OD Edge Dummy Gate Delay Circuits for DAC Skew Calibration
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Solution Overview
Problem
The need for a low-cost, area-efficient delay circuit design to address skew issues in semiconductor devices, particularly in DACs, due to varying switch driver loads and layout differences among DAC cell segments, which compromise data fidelity and accuracy.
Innovation Solution
Reusing oxide diffusion (OD) edge dummy gates to implement tunable delay circuits that reduce the length of oxide diffusion (LOD) effect and address skew by employing gate delay tuning or capacitive load tuning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate delay circuits are designed to address skew issues, then skew calibration capability is improved, but area overhead increases
Solution Approach 1:
The patent makes OD edge dummy gates serve dual purposes: their primary function of reducing LOD effect and their secondary function as delay circuits for skew calibration. By configuring these dummy gates with tap nodes connected to delay circuit inputs/outputs, the same structural elements perform both LOD mitigation and delay adjustment, eliminating the need for separate delay circuit blocks and thus reducing area overhead while maintaining skew calibration capability
Solution Approach 2:
The patent recovers and repurposes the OD edge dummy gates that would otherwise be discarded or underutilized elements. Instead of treating them as mere placeholders for LOD reduction, the invention extracts their functional potential by adding tap nodes and configuring them as active delay circuit components, thereby transforming wasted structural elements into useful delay calibration resources that reduce overall area requirements
2Measurement precision
If delay circuits are implemented using traditional designs, then skew calibration is achieved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by making existing OD edge dummy gates multi-functional. These gates simultaneously perform LOD reduction and delay circuit operations through tap node configurations. This eliminates the need for separate delay circuit blocks, reducing overall circuit complexity while maintaining full skew calibration capability across all DAC cell segments
Solution Approach 2:
The OD edge dummy gates serve themselves by providing both their original function (LOD reduction) and an additional function (delay calibration) without requiring external dedicated structures. The tap nodes are configured to utilize the existing dummy gate structures, allowing the device to self-calibrate skew using its own inherent structural elements rather than requiring separate calibration circuitry
Data Source
AI summary
A semiconductor device includes an oxide diffusion (OD) area; at least one first poly gate, formed above the OD area; and a plurality of second poly gates, formed on both sides of the at least one first poly gate and above the OD area. The plurality of second poly gates are OD edge dummy gates that are used to reduce length of oxide diffusion (LOD) effect, and at least a portion of the plurality of second poly gates are reused to implement at least one delay circuit.