Dummy Gate Electrode Shape for FinFET Residue Control
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Solution Overview
Problem
In the fabrication of FinFETs, the decreasing spacing between vertical fins exacerbates issues such as unwanted residues between the fin edge and the dummy gate electrode, leading to device instability and potential failure, particularly when using a fixed etching process that results in a dummy gate electrode configuration with a base broader than the fin, which can generate residues.
Innovation Solution
A method involving a two-stage etching process is employed to form a dummy gate electrode with a broader base than the bottom, ensuring the dummy gate electrode does not overlap with the fin edge, thereby reducing residue formation and enhancing device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed etching process is used to form the dummy gate electrode, then the fabrication process is simple, but unwanted residues are generated between the fin edge and the dummy gate electrode
Solution Approach 1:
The patent applies parameter changes by modifying the etching process parameters - specifically using a two-step etching process with different etching conditions. The first etching step uses parameters that create an initial dummy gate electrode structure, while the second etching step uses adjusted parameters to precisely define the final dummy gate electrode position and shape, eliminating residues without compromising process simplicity
Solution Approach 2:
The patent segments the etching process into two distinct steps: a first etching step that forms an initial dummy gate electrode structure, and a second etching step that precisely defines the final dummy gate electrode. This segmentation allows each step to be optimized independently, achieving both manufacturing precision and process efficiency
2Ease of operation
If the dummy gate electrode has a base broader than the fin, then the etching process is easier to control, but residues are generated between the fin edge and the dummy gate electrode
Solution Approach 1:
The patent applies local quality by creating a dummy gate electrode with non-uniform width - the base is broader than the top portion. This local variation in dimensions allows the broader base to provide etching process control while the narrower top portion prevents residue formation between the fin edge and dummy gate electrode, effectively resolving the contradiction through spatially differentiated geometry
3Productivity
If the spacing between vertical fins is decreased to increase device density, then higher device density is achieved, but the likelihood of device instability and failure increases due to residue formation
Solution Approach 1:
The patent changes the etching process parameters to a two-step process with optimized conditions that enable precise formation of the dummy gate electrode even at reduced fin spacing. This allows higher device density to be achieved while maintaining device reliability by eliminating the residue formation issue that typically occurs at smaller spacings
Data Source
AI summary
The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.