Dummy Gate ESD Device Epitaxial Uniformity
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Solution Overview
Problem
Integrated circuits are susceptible to damage from electrostatic discharges due to high current densities that can burn away silicide material and cause non-uniformity in epitaxially grown structures during the formation of ESD devices, particularly when silicide is formed over source or drain regions and during epitaxial growth processes.
Innovation Solution
The implementation of dummy gates between real gates in integrated circuits, which reduces the epitaxial window and ensures uniformity of active regions, thereby minimizing the loading effect and preventing damage from high electric currents, while avoiding silicide formation over source or drain regions adjacent to the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide is formed over source or drain regions to facilitate efficient current conduction, then electrical conductivity is improved, but the high current density from ESD can burn away the silicide and surrounding material causing damage
Solution Approach 1:
The patent extracts silicide formation from the source and drain regions adjacent to the gate, preventing silicide from being present in these critical areas. This is achieved by selectively forming silicide only in regions away from the gate-adjacent source/drain areas, thereby eliminating the harmful effect of silicide burnout during ESD events while preserving current conduction paths in safe regions
Solution Approach 2:
The patent applies different material properties to different regions: silicide is formed in regions where it provides beneficial conductivity without exposing it to high ESD current density, while gate-adjacent source/drain regions are kept free of silicide to prevent burnout. This spatial differentiation of material quality optimizes both conductivity and ESD resistance
2Manufacturing precision
If dummy gates are added between real gates to reduce the epitaxial window and ensure uniformity, then epitaxial growth uniformity is improved, but device complexity increases
Solution Approach 1:
The patent uses dummy gates as simplified copies of real gates that perform only the structural function of defining epitaxial windows without the full functionality of active gates. These dummy gate structures replicate the essential geometry needed to create uniform epitaxial regions while being electrically inactive, thus adding minimal complexity compared to fully functional gates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of epitaxial growth, reduces the risk of damage from electrostatic discharges, and optimizes the performance of ESD devices by allowing higher electric currents to pass through while maintaining structural integrity and reducing thermal issues.
Implementation Method 1
Another issue involving the formation of ESD devices arises when the source drain regions are formed through an epitaxial growth process. An epitaxial growth process involves growing a semiconductor crystal onto an existing crystal.
Implementation Method 2
Electronic devices that utilize integrated circuits are susceptible to electrostatic discharges (ESDs). An electrostatic discharge may occur from a human holding the device or other source.
Data Source
AI summary
An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.