Polysilicon Dummy Gate Etching Residue Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing lies in controlling the etching of polysilicon dummy gates with non-uniform crystal orientations, leading to significant gate material residue issues that affect manufacturing yield and device performance in the replacement metal gate (RMG) process.
Innovation Solution
An impurity treatment is performed on the gate material layer or dummy gate, either before or after forming the dummy gate, using a patterned mask layer to create doped or treated regions, which enhances the etching process and addresses the residue issue by influencing crystallization and etching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thermal processes are performed to transform amorphous silicon to polysilicon in dummy gates, then the gate material structure is improved for metal gate replacement, but the crystal orientations of polysilicon grains become non-uniform and uncertain making etching control difficult
Solution Approach 1:
The patent applies preliminary action by performing impurity treatment on the gate material layer before the etching process to create doped regions. This pre-treatment modifies the material properties in advance, ensuring that when etching occurs later, the process can be properly controlled even after thermal transformation creates non-uniform crystal orientations. The impurity treatment is done at a specific timing point before dummy gate removal to prevent residue issues.
Solution Approach 2:
The patent applies local quality by creating doped regions with different impurity concentrations in specific areas of the gate material layer through patterned mask layers. This results in treated regions with modified etching characteristics, allowing different parts of the dummy gate to be etched at different rates. This local differentiation enables precise control over the etching process, addressing the non-uniform crystal orientation problem by creating intentionally non-uniform doping profiles that compensate for the random crystal grain structures.
2Productivity
If dummy gates are removed after thermal processes, then the metal gate replacement process can proceed, but significant gate material residue remains affecting manufacturing yield and device performance
Solution Approach 1:
The patent applies parameter changes by modifying the chemical composition and physical properties of the gate material layer through impurity treatment. By introducing dopants and changing the material parameters (doping concentration, crystal structure, etching rate), the etching process can selectively remove dummy gate material without leaving residues. The parameter changes are timed to occur before dummy gate removal, ensuring clean elimination of the dummy structures while enabling subsequent metal gate formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The impurity treatment improves the etching process efficiency, effectively reducing gate material residue and enhancing manufacturing yield by controlling the crystallization and etching rates of polysilicon grains, even when crystal orientations are non-uniform.
Implementation Method 1
An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer
Implementation Method 2
The crystallization of the gate material layer may be influenced by the impurity treatment, and some of the crystal orientations in the dummy gate may be destroyed by the impurity treatment
Implementation Method 3
An etching process is performed to remove the gate material layer including the doped region
Data Source
AI summary
A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.