Dummy Gate High Voltage Transistor HCI Mitigation
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Solution Overview
Problem
Existing methods for fabricating high voltage semiconductor transistors face challenges in controlling hot carrier injection (HCI) and time-dependent dielectric breakdown (TDDB) due to the decreasing geometry size, which affects the reliability and performance of the devices.
Innovation Solution
The implementation of a counter doped region in the drift region, separated by dummy gate structures, which reduces the proximity of dopants to the gate structure, thereby minimizing on-state resistance and junction leakage current, and improves the operating voltage window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain region is pushed away from the gate and source region to achieve large voltage drop, then the voltage drop requirement is met, but the device size increases and geometry scaling becomes impractical
Solution Approach 1:
The drift region is segmented into multiple regions with different doping concentrations (first drift region with lower doping, second drift region with higher doping). This segmentation allows the device to achieve the required voltage drop across the segmented regions without requiring a single excessively long drift region, enabling geometry scaling while maintaining high voltage capability.
Solution Approach 2:
Different regions of the drift zone are assigned different doping qualities - the first drift region has lower doping concentration optimized for voltage blocking, while the second drift region has higher doping concentration optimized for carrier transport. This local quality differentiation allows compact device design with sufficient voltage drop.
2Reliability
If the counter doped region is placed close to the gate structure to reduce on-state resistance, then the on-state resistance decreases, but hot carrier injection and junction leakage current increase
Solution Approach 1:
A lightly doped intermediate drift region is introduced between the counter doped region and the gate structure. This intermediate region acts as a buffer that allows the counter doped region to be positioned closer to the gate for lower on-state resistance, while the lightly doped intermediate zone prevents direct interaction that would cause hot carrier injection and junction leakage.
3Productivity
If the geometry size is decreased to increase functional density, then the chip area utilization improves, but the control of hot carrier injection and TDDB becomes more difficult
Solution Approach 1:
The drift region is divided into segmented zones with different doping concentrations arranged in a vertical stack. This segmentation allows compact lateral footprint (enabling high functional density) while maintaining sufficient vertical distance for voltage blocking and reliability control through the multi-zone doping profile.
Solution Approach 2:
The solution transitions from lateral extension (horizontal scaling) to vertical stacking (vertical dimension). By arranging drift regions with different doping concentrations in vertical layers, the patent achieves high functional density in the lateral plane while maintaining adequate voltage drop and reliability control in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases HCI and TDDB while maintaining device performance by ensuring the counter doped region is sufficiently far from the gate structure, enhancing the knee region of the Id-Vd curve and increasing the operating voltage window.
Implementation Method 1
The implementation of a counter doped region in the drift region, separated by dummy gate structures, which reduces the proximity of dopants to the gate structure, thereby minimizing on-state resistance and junction leakage current
Implementation Method 2
The implementation of a counter doped region in the drift region, separated by dummy gate structures, which reduces the proximity of dopants to the gate structure, thereby minimizing on-state resistance and junction leakage current, and improves the operating voltage window. This approach effectively decreases HCI and TDDB
Data Source
AI summary
A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate.