Dummy Gate Implantation for Low-Distortion FinFET Patterning
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing semiconductor devices with reduced distortion of gates due to compressive stress in dummy gate layers, leading to line width variations and performance issues during the patterning process.
Innovation Solution
The method involves implanting a dummy gate layer with dopants to form an implantation region, which reduces stress and improves distortion, allowing for precise patterning and subsequent replacement with a metal gate structure, thereby minimizing line width variations and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the geometry size is scaled down to increase functional density, then production efficiency is improved and costs are lowered, but stress differences in dummy gate layers increase causing distortion of gate electrodes
Solution Approach 1:
The patent applies local quality by creating an implantation region with different stress characteristics within the dummy gate layer. Specifically, a first portion of the dummy gate layer is implanted with dopants to form a region with neutral stress, while a second portion remains unimplanted or differently implanted. This local differentiation of material properties allows the stressed dummy gate layer to be patterned with reduced distortion, thereby maintaining manufacturing precision even as geometry scales down for improved productivity.
Solution Approach 2:
The patent employs parameter changes by modifying the stress state of the dummy gate layer through selective dopant implantation. By changing the concentration and distribution of dopants in specific regions of the dummy gate layer, the stress parameters are adjusted to reduce the overall stress difference. This parameter modification enables accurate patterning of gate structures at scaled-down dimensions without the distortion that would otherwise occur due to stress.
2Manufacturing precision
If the dummy gate layer is patterned with high stress difference, then the patterning process becomes more challenging, but skipping stress management would simplify the process
Solution Approach 1:
The patent applies preliminary action by performing dopant implantation on the dummy gate layer before the patterning process. This pre-treatment modifies the stress distribution in the dummy gate layer, creating regions with neutral stress that will maintain their dimensional integrity during subsequent patterning. By addressing the stress issue beforehand, the actual patterning process becomes more reliable and achieves better alignment precision without requiring excessively complex in-situ stress management techniques.
Solution Approach 2:
The patent uses the implantation region as an intermediary between the inherently stressed dummy gate layer and the patterning process. The selectively implanted region acts as a buffer or mediator that absorbs or compensates for the stress, allowing the patterning tools to work with a more stable substrate. This intermediary structure enables accurate pattern transfer while avoiding the need for overly complex patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces stress in dummy gate layers, resulting in improved distortion and reduced line width variations, leading to better gate structure formation and performance in semiconductor devices.
Implementation Method 1
performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer
Data Source
AI summary
A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; etching back the dummy gate layer; performing an implantation process to the dummy gate layer to form an implantation region in the dummy gate layer, wherein a vertical thickness of the dummy gate layer is greater than a vertical thickness of the implantation region; forming a patterned hard mask stack over the implantation region; patterning the implantation region and the dummy gate layer by using the patterned hard mask stack as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.