Dummy Gate Interlayer Dielectric Coplanar Formation
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Solution Overview
Problem
The reduction in critical dimensions of static random access memory (SRAM) cells complicates the fabrication of semiconductor structures, particularly in forming interlayer dielectric layers and gate structures, leading to difficulties in transistor performance and SRAM cell functionality.
Innovation Solution
A semiconductor structure and fabrication method involving a base substrate with distinct regions, where a dummy gate structure extends through these regions, allowing for the formation of doped source/drain regions and an interlayer dielectric layer with a top surface coplanar to the dummy gate, which eases the formation of the interlayer dielectric layer without compromising the space for transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the critical dimensions of SRAM are reduced to increase integration level, then the density and capacity of memory devices are improved, but the fabrication difficulty and process complexity increase significantly
Solution Approach 1:
The patent divides the gate structure formation into distinct segments: first forming a dummy gate structure that spans across the third region, then selectively removing portions of it. This segmentation allows different regions to be processed independently, reducing the overall fabrication difficulty despite reduced critical dimensions
Solution Approach 2:
The dummy gate structure is formed preliminarily before the final gate structure. This preliminary structure serves as a placeholder that simplifies subsequent processing steps, particularly in forming the interlayer dielectric layer and source/drain regions, by providing a defined reference structure early in the fabrication process
2Productivity
If the critical dimensions are reduced, then more transistors can be integrated in the same area, but the precision required for forming interlayer dielectric layers and gate structures increases
Solution Approach 1:
The dummy gate structure acts as an intermediary element that simplifies the formation of the interlayer dielectric layer. By having this intermediate structure in place, the dielectric layer can be formed with standard precision techniques rather than requiring ultra-precise alignment, thus maintaining manufacturing precision while achieving high integration density
Solution Approach 2:
The patent applies different structural qualities to different regions: the dummy gate structure provides a uniform reference plane across the third region, while the first and second regions receive specialized processing for their respective gate structures. This local differentiation allows precise control in critical areas while maintaining overall integration density
3Ease of manufacture
If space is allocated for interlayer dielectric layer formation, then the fabrication process is simplified, but the space available for transistor structures is reduced
Solution Approach 1:
The dummy gate structure merges multiple functions: it serves as a placeholder for the future gate structure, provides a reference plane for interlayer dielectric layer formation, and defines the boundaries of the third region. This merging allows the dielectric layer to be formed easily within the same space that will eventually contain the transistor structures, eliminating the need for additional dedicated space
Data Source
AI summary
Semiconductor structure and fabrication method are provided. The method includes: providing a base substrate including a first region, a second region and a third region between the first and the second region; forming a dummy gate structure extending from the first region to the second region and through the third region; forming first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region; forming second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region; forming an opening in the dummy gate structure in the third region and exposing the base substrate in the third region; and forming an interlayer dielectric layer within the opening to have a top surface coplanar with the dummy gate structure.