Dummy Gate Ion Doping for HKMG Planarization Control
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Solution Overview
Problem
Transistors formed using silicon oxide or silicon oxynitride as gate dielectric materials face issues with leakage current and impurity diffusion, leading to unreliable and unstable performance due to poor morphology and dimensional control in high-K metal gate (HKMG) transistors formed by the gate-last process.
Innovation Solution
A method involving the formation of a dummy gate film on a substrate, where the upper portion is ion-doped to create a modified film with a higher planarization rate than the dielectric film, allowing for precise control of the dielectric layer thickness and avoiding surface recesses, ensuring accurate dimensions and stable performance by preventing residue metal deposition and short contacts between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon oxide or silicon oxynitride is used as gate dielectric material, then the transistor can be formed with simple material selection, but leakage current increases and impurity diffusion occurs leading to poor reliability
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric material from low-K (silicon oxide/silicon oxynitride) to high-K (hafnium oxide, tantalum oxide, or their alloys with dielectric constant ≥4). This parameter change enables reduced gate leakage current while maintaining effective gate control, directly resolving the contradiction between reliability and harmful leakage factors.
2Loss of energy
If high-K metal gate (HKMG) transistor is formed by gate-last process, then leakage current and power consumption are reduced, but morphology and dimensional control deteriorate
Solution Approach 1:
The patent performs preliminary doping of the dummy gate film before the gate-last process to create a modified layer with enhanced planarization characteristics. This preliminary action ensures that subsequent CMP processing achieves proper dielectric layer thickness and surface flatness, preventing dimensional control issues while maintaining the energy-saving benefits of the gate-last process.
Solution Approach 2:
The patent introduces a modified dummy gate layer as an intermediary element between the substrate and the final metal gate. This intermediary layer with controlled planarization rate serves as a sacrificial structure that enables precise dielectric layer formation, resolving the contradiction between energy efficiency and manufacturing precision.
3Shape
If dummy gate film is planarized with dielectric film, then surface flatness is achieved, but difficulty in controlling dielectric layer thickness occurs due to similar planarization rates
Solution Approach 1:
The patent creates local quality differentiation by doping only the upper portion of the dummy gate film to form a modified layer with distinct planarization characteristics. This modified layer has a planarization rate different from both the dummy gate film and the dielectric film, enabling selective removal and precise dielectric layer thickness control while maintaining overall surface flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in transistors with desirable morphologies, stable performance, and improved reliability by ensuring accurate control of the gate dielectric and metal gate thickness, reducing leakage current and power consumption while enhancing transistor performance.
Implementation Method 1
An upper portion of the dummy gate film is doped to be converted into a modified film on a remaining dummy gate film
Implementation Method 2
The dielectric film and the modified layer are planarized to provide a dielectric layer, and to remove the modified layer and expose the dummy gate layer
Data Source
AI summary
Transistor devices and fabrication methods are provided. A transistor is formed by forming a dummy gate film on a substrate and doping an upper portion of the dummy gate film to form a modified film. The modified film and the remaining dummy gate film are etched to form a modified layer and a dummy gate layer on the substrate. Source/drain regions are formed in the substrate and on both sides of the dummy gate layer. A dielectric film is formed on each of the substrate, the source/drain regions, and the dummy gate layer. The dielectric film and the modified layer are planarized to provide a dielectric layer, and to remove the modified layer and expose the dummy gate layer. The dielectric film has a planarization rate lower than the modified layer, and the formed dielectric layer has a surface higher than the exposed dummy gate layer.