Dummy Gate Isolation for FDSOI Leakage Reduction
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Solution Overview
Problem
Fully depleted silicon-on-insulator (FDSOI) devices with gate first processing face issues of higher leakage and area loss due to continuous shallow trench isolation (STI) and the need for active layer fillers, which decrease available space and increase leakage.
Innovation Solution
A physical diffusion break is formed using a shallow/selective spacer etching process, creating openings around a dummy gate to isolate metal gates and removing spacers and portions of the source/drain regions, thereby avoiding continuous active layer fillers and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous shallow trench isolation (STI) dummy gate tie down to voltage drain is used, then circuit isolation is formed, but voltage leakage increases and area is lost
Solution Approach 1:
The continuous STI dummy gate is segmented into discrete sections by introducing physical diffusion breaks at strategic locations. This segmentation interrupts the continuous conductive path that causes leakage while maintaining isolation functionality in each segment. The dummy gate is divided into multiple isolated regions rather than forming a continuous tie-down structure.
Solution Approach 2:
The harmful continuous conductive path is extracted and removed from the structure. By taking out the continuous STI material and replacing it with a patterned structure that includes air gaps or insulating material, the leakage path is eliminated while retaining the necessary isolation function.
2Reliability
If continuous shallow trench isolation (STI) dummy gate is used, then circuit isolation is formed, but available area decreases
Solution Approach 1:
The dummy gate structure is segmented to eliminate the need for continuous STI filler material. By introducing physical diffusion breaks and using a patterned dummy gate approach, the structure occupies less area while maintaining effective circuit isolation. The segmented design removes unnecessary material that would otherwise consume valuable device area.
3Reliability
If active layer filler such as STI is inserted, then voltage source is separated between drains, but device area decreases
Solution Approach 1:
The dummy gate structure is designed to perform multiple functions simultaneously: it provides circuit isolation, establishes voltage separation between drains, and maintains structural integrity without requiring additional filler material. This multi-functional design eliminates the need for separate active layer filler structures, thereby conserving device area.
Data Source
AI summary
The present disclosure relates to an isolation region between semiconductor devices and methods of fabrication. Embodiments include device having a silicon-on-insulator (SOI) substrate; a dummy gate between two metal gates formed over the SOI substrate, the dummy gate providing a physical diffusion break between the two metal gates; raised source/drain (S/D) regions formed on sides of the metal gates; and interlayer dielectric formed over the dummy gate, raised S/D regions and metal gates and in openings on sides of the dummy gate.