Dummy Gate Isolation Structure for Metal Gate CMOS Formation
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Solution Overview
Problem
MOS devices with polysilicon gate electrodes suffer from the poly depletion effect, which increases the effective gate dielectric thickness and makes it difficult to create an inversion layer at the semiconductor surface.
Innovation Solution
The formation of metal gate electrodes or metal silicide gate electrodes addresses the poly depletion problem by using metallic gates with band-edge work functions in NMOS and PMOS devices, and the process involves etching a dummy gate, filling the opening with dielectric layers, and performing planarization and etching processes to create gate isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate electrodes are used, then the gate structure is simple to form, but the poly depletion effect increases the effective gate dielectric thickness and makes it difficult to create an inversion layer
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, titanium nitride, or other metal gate materials). This material substitution fundamentally alters the electrical properties, eliminating the poly depletion effect while maintaining gate functionality. The metal gate provides better control over the inversion layer formation due to its superior electrical conductivity and absence of depletion layers.
2Reliability
If metal gate electrodes are formed to solve poly depletion, then inversion layer formation is improved, but the manufacturing process becomes more complex requiring dummy gate etching and dielectric filling
Solution Approach 1:
The patent employs a preliminary dummy gate structure that is formed before the metal gate. This dummy gate serves multiple purposes: it defines the gate pattern early in the process, protects underlying structures during subsequent processing steps, and provides a template for the final metal gate formation. The dummy gate is later removed and replaced with the metal gate material, allowing complex metal gate formation while maintaining process control.
Solution Approach 2:
The dummy gate acts as an intermediary structure between the initial process steps and the final metal gate formation. It mediates the transition by providing a temporary structure that facilitates pattern transfer and process alignment, then is removed to allow metal gate deposition. This intermediary approach simplifies the overall manufacturing by breaking down the complex metal gate formation into manageable steps.
3Reliability
If dual-gate CMOS devices are used for different work function requirements, then both NMOS and PMOS devices achieve optimal performance, but the device structure and process complexity increases
Solution Approach 1:
The patent applies different metal gate materials or different metal layer compositions to specific device regions. For example, NMOS devices may receive a metal gate with lower work function (such as titanium nitride) while PMOS devices receive a metal gate with higher work function (such as tungsten or tantalum nitride). This localized material differentiation allows each device type to achieve optimal work function matching with its channel, improving carrier injection and threshold voltage control without requiring separate gate structures.
Solution Approach 2:
The patent employs composite metal gate structures consisting of multiple metal layers with different properties. For instance, a stack of titanium nitride and tungsten, or tantalum nitride and tungsten, combines the benefits of different materials: one layer provides the appropriate work function while another layer provides good adhesion, stress control, or barrier properties. This composite approach achieves the desired electrical characteristics while maintaining a unified gate structure that simplifies manufacturing compared to completely separate dual-gate designs.
Data Source
AI summary
A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.