Dummy Gate Overlap on Isolation Regions to Prevent MOSFET Leakage

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Solution Overview

Problem

The scaling down of semiconductor devices, such as MOSFETs, leads to challenges in device packing density and performance due to leakage issues caused by improperly formed epitaxial features adjacent to dummy gates.

Innovation Solution

The configuration of semiconductor devices is adjusted to improve the formation of epitaxial features by ensuring that dummy gates overlap with isolation regions, preventing exposure of the isolation region surfaces during epitaxial growth, and thereby enhancing the uniformity and volume of the epitaxial features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device geometry is scaled down to increase production efficiency, then productivity is improved, but leakage issues worsen due to improperly formed epitaxial features

Engineering Contradiction:
Improveproduction efficiencyVSAvoidleakage issue
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The dummy gate is formed to overlap with the isolation region before epitaxial growth occurs. This preliminary structural configuration prevents the epitaxial material from directly contacting the isolation region surface, thereby preventing leakage paths from forming during subsequent processing steps while allowing continued device scaling for high productivity

Inventive Principle:
Principle #10Preliminary action

2Reliability

If dummy gates are positioned to overlap isolation regions to prevent leakage, then reliability is improved, but device complexity increases due to configuration adjustments

Engineering Contradiction:
Improveleakage preventionVSAvoidconfiguration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy gate structure is merged with the isolation region by positioning the dummy gate to overlap the isolation region. This combination creates a unified structure that simultaneously serves as a dummy gate for epitaxial feature formation and provides leakage prevention by blocking direct contact between epitaxial material and the isolation region, thereby improving reliability without proportionally increasing device complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves device performance by reducing leakage issues, achieving more uniform electrical properties, and ensuring proper contact between conductive contacts and epitaxial features.

Implementation Method 1

preventing exposure of the isolation region surfaces during epitaxial growth

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS12308279B2Semiconductor device including an isolation region having an edge being covered and manufacturing method for the same
Publication Date: 2025.05.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12308279B2 patent drawing
  • US12308279B2 patent drawing
  • US12308279B2 patent drawing

AI summary

The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.