Dummy Gate Isolation Structure for Poly Depletion Reduction
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Solution Overview
Problem
Metal-Oxide-Semiconductor (MOS) devices with polysilicon gate electrodes suffer from carrier depletion effects, known as poly depletion, which increase the effective gate dielectric thickness and make it difficult to create an inversion layer at the semiconductor surface, limiting the performance of MOS devices.
Innovation Solution
The formation of gate isolation regions involves etching a dummy gate, filling the opening with dielectric layers, and performing planarization processes to create a concave top-view shape, allowing for the replacement of dummy gates with metal gates that have appropriate work functions for NMOS and PMOS devices, addressing the poly depletion issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate electrodes are used in MOS devices, then the gate electrode can be formed with standard doping operations, but carrier depletion effects occur which increase the effective gate dielectric thickness and make it difficult to create an inversion layer
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal (such as tungsten, titanium nitride, or other metal materials). This parameter change eliminates the carrier depletion effect inherent in polysilicon while maintaining the ability to form a functional gate electrode with appropriate work function, thereby resolving the contradiction between ease of manufacture and reliability of inversion layer creation.
Solution Approach 2:
The patent employs composite gate structures consisting of metal gate electrodes combined with high-k dielectric materials. This composite approach replaces the depleted polysilicon gate with a metal gate that does not exhibit carrier depletion, while the high-k dielectric provides the necessary electrical insulation and field control, together achieving both manufacturability and reliable inversion layer formation.
2Reliability
If metal gate electrodes are formed to solve poly depletion, then the carrier depletion effect is eliminated, but a complex multi-step process is required including dummy gate formation, etching, dielectric filling, and planarization
Solution Approach 1:
The patent employs a preliminary dummy gate structure that is formed before the metal gate electrode. This dummy gate serves as a placeholder that defines the gate region and allows subsequent processing steps (etching, dielectric filling, planarization) to be performed in a controlled sequence. The preliminary action of forming the dummy gate simplifies the overall process by providing a reference structure for alignment and pattern transfer.
Solution Approach 2:
The gate formation process is segmented into distinct stages: dummy gate formation, dummy gate etching, dielectric filling, planarization, and metal gate electrode formation. This segmentation allows each step to be optimized independently and enables better process control, reducing the complexity of the overall multi-step process required to achieve reliable metal gate electrodes.
3Reliability
If dual-gate CMOS devices are used to provide band-edge work functions for NMOS and PMOS, then the poly depletion problem is solved, but the device structure becomes more complex
Solution Approach 1:
The patent applies local quality by using different metal materials for NMOS and PMOS gate electrodes. Each gate electrode is tailored with a specific metal material that provides the appropriate work function for its respective device type (n-type or p-type). This localized material selection achieves the required work function control without needing dual-gate structures, thereby reducing device complexity while maintaining reliability.
Data Source
AI summary
A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.