Dummy Gate Electrode Parasitic Capacitance Reduction
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Solution Overview
Problem
The operational speed of semiconductor devices is hindered by parasitic capacitance between conductive layers and interconnects, and variations in oscillation frequency are uncontrolled due to high aspect ratios and parasitic capacitance between drain regions and gate electrodes, which are not adequately addressed by existing technologies.
Innovation Solution
The semiconductor device incorporates dummy gate electrodes maintained at the same potential as source regions, allowing for more flexible and regular arrangement of gate electrodes, reducing parasitic capacitance and aspect ratios, thereby enhancing controllability and operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operational speed of the oscillator circuit is increased, then the oscillation frequency exceeds 1 GHz, but parasitic capacitance between conductive layers and interconnects prevents further speed improvement
Solution Approach 1:
The patent extracts and removes the gate electrode from above the source region, creating a dummy gate structure. This extraction eliminates the parasitic capacitance between the gate electrode and source region, allowing operational speed to increase beyond 1 GHz without the limiting capacitive effect
Solution Approach 2:
The gate electrode structure is segmented into two parts: a normal gate electrode positioned only over the channel region, and a separate dummy gate electrode positioned over the source region. This segmentation allows the normal gate to control the transistor while the dummy gate eliminates parasitic capacitance, resolving the speed-capacitance contradiction
2Device complexity
If the gate electrode is positioned directly over the source region to simplify structure, then device complexity is reduced, but oscillation frequency varies widely causing uncontrollable variations
Solution Approach 1:
The dummy gate electrode acts as an intermediary element between the normal gate electrode and the source region. It mediates the electrical field distribution, eliminating parasitic capacitance effects while maintaining structural simplicity. This intermediary structure stabilizes oscillation frequency without complicating the overall device architecture
Data Source
AI summary
A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and a corresponding one of the source regions. A plurality of dummy gates are provided each between adjacent two of the MOS transistors. The dummy gate electrodes are maintained at an equi-potential with the adjacent drain regions. MOS transistors include a row of pMOS transistors and nMOS transistors, wherein each of pMOS transistors and a corresponding nMOS transistor configure a CMOS gate, and a plurality of CMOS gates configure a ring oscillator.