Dummy Gate Profile Control for FinFET Replacement Gate Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes, existing processes face challenges that need to be addressed to improve integration density and device performance.
Innovation Solution
The formation of dummy gates using multiple etching steps, with controlled parameters such as passivation gas flow rate, pulsed voltage bias duty cycle, and plasma generation power, allows for the tuning of the dummy gate profile shape to improve process yield and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but additional process problems arise that worsen manufacturing precision and reliability
Solution Approach 1:
The etching process is divided into multiple sequential etching steps, each with controlled parameters, to form the dummy gate profile in stages. This segmentation allows precise control over the final profile shape while maintaining manufacturing precision despite reduced feature sizes
Solution Approach 2:
The patent controls the dummy gate profile shape by adjusting etching parameters including passivation gas flow rate, pulsed voltage bias duty cycle, and plasma generation power across multiple etching steps. These parameter changes enable precise profile control that maintains manufacturing precision even as minimum feature sizes are reduced to improve integration density
2Reliability
If dummy gate profile shape is controlled through multiple etching steps with adjusted parameters, then device performance is improved, but process complexity increases
Solution Approach 1:
The complex profile control requirement is resolved by segmenting the etching process into multiple steps, each with specific parameter settings. This segmentation transforms a single complex operation into manageable sequential steps, improving device performance through precise profile control while making the overall process more controllable
Solution Approach 2:
Instead of using a single complex etching step, the patent employs parameter changes across multiple etching steps (passivation gas flow rate, pulsed voltage bias duty cycle, plasma generation power) to achieve the desired profile shape. This approach improves device performance through precise control while the systematic parameter adjustment makes the complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the control of the dummy gate profile shape, which in turn improves the formation of replacement gate stacks, reducing processing defects and enhancing device performance.
Implementation Method 1
performing a first plasma etching process including a first pulsed bias voltage
Implementation Method 2
plasma etching process
Data Source
AI summary
A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.