Dummy Gate Profile Control in Gate-Last MOSFET Process
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Solution Overview
Problem
In the gate-last process for MOSFET manufacturing, the critical dimension and profile of the dummy gate cannot be accurately controlled at the 22 nm node and beyond, leading to degraded gate Line Edge Roughness (LER), device performance, and reliability.
Innovation Solution
A method involving the deposition of a gate oxide layer, bottom-layer amorphous silicon, an oxide-nitride-oxide structured hard mask, and subsequent etching using photoresist lines to form a dummy gate with precise dimensions, improving control over the dummy gate's critical dimension and profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate-last process is used, then metal gate electrode can be formed, but the critical dimension and profile of the dummy gate cannot be accurately controlled
Solution Approach 1:
The dummy gate structure is segmented into multiple layers: gate oxide layer, bottom-layer amorphous silicon, ONO structured hard mask, and top-layer amorphous silicon. This segmentation allows each layer to be precisely controlled independently, achieving accurate critical dimension and profile control that cannot be obtained with conventional single-layer dummy gates.
Solution Approach 2:
The ONO structured hard mask is deposited on the bottom-layer amorphous silicon before forming the final dummy gate structure. This preliminary action establishes a precise mask pattern that defines the critical dimensions, ensuring accurate control before subsequent etching and material removal steps.
2Manufacturing precision
If conventional gate-last process is used, then metal gate electrode can be formed, but the profile of the dummy gate cannot be accurately controlled
Solution Approach 1:
The multi-layer structure with distinct functional layers (gate oxide, bottom-layer amorphous silicon, ONO hard mask, top-layer amorphous silicon) enables independent optimization of each layer's profile characteristics, achieving precise overall dummy gate profile control.
Solution Approach 2:
The patent employs specific thickness parameters for each layer (gate oxide: 50-150nm, bottom-layer amorphous silicon: 100-300nm, ONO hard mask: 50-150nm, top-layer amorphous silicon: 100-300nm) to precisely control the dummy gate profile. These parameter changes enable accurate profile definition that conventional processes cannot achieve.
3Productivity
If conventional gate-last process is used, then manufacturing process can be completed, but gate LER is degraded
Solution Approach 1:
The ONO structured hard mask acts as an intermediary layer between the amorphous silicon layers and the etching process. This intermediary provides a stable, precisely controllable mask pattern that transfers accurate dimensions to the dummy gate structure, reducing line edge roughness while maintaining manufacturing productivity.
Solution Approach 2:
The dummy gate structure uses composite materials including gate oxide, amorphous silicon, and ONO hard mask layers. This composite structure combines the advantages of each material: gate oxide provides electrical isolation, amorphous silicon provides structural integrity, and ONO hard mask provides precise patterning, collectively reducing gate LER.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively improves the accuracy of the dummy gate's critical dimension and profile, enhancing gate LER, device performance, and reliability.
Implementation Method 1
growing a gate oxide layer on the semiconductor substrate
Implementation Method 2
depositing bottom-layer amorphous silicon (α-Si) on the gate oxide layer
Implementation Method 3
depositing an oxide-nitride-oxide (ONO) structured hard mask on the bottom-layer α-Si
Implementation Method 4
forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer
Implementation Method 5
etching the hard mask layer, the top-layer α-Si, the ONO structured hard mask and the bottom-layer α-Si in accordance with the photoresist lines
Data Source
AI summary
A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.