Dummy Gate Sidewall Protection for Fin Transistor Isolation
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Solution Overview
Problem
In the fabrication of fin-based transistors, residual dummy gate material can cause electrical shorting between source/drain regions and metal gate structures, leading to defects and reduced yield.
Innovation Solution
A sidewall protection layer is formed on the sidewall spacers of the dummy gate structure before etching the fin structure to form source/drain recesses, minimizing contact with residual dummy gate material and preventing electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If residual dummy gate material remains after etching, then the dummy gate structure can be removed, but electrical shorting occurs between source/drain regions and metal gate structures
Solution Approach 1:
A sidewall protection layer is introduced as an intermediary between the source/drain regions and the dummy gate structure. This protection layer prevents direct contact between etched material and the dummy gate, eliminating the harmful electrical shorting effect while allowing the dummy gate to be removed.
Solution Approach 2:
The sidewall protection layer is formed in advance on the sidewall spacers before the source/drain recess etching process. This preliminary protective action prevents the etching process from creating electrical shorts between source/drain regions and dummy gate material, addressing the harmful effect before it can occur.
2Productivity
If the fin structure is etched to form source/drain recesses, then source/drain regions can be formed, but residual dummy gate material causes defects
Solution Approach 1:
The sidewall protection layer acts as a mediator that defines the etching boundary. It enables precise formation of source/drain recesses by preventing lateral etching into the dummy gate region, thereby improving manufacturing precision without reducing productivity.
3Ease of manufacture
If no sidewall protection layer is formed, then the process is simpler, but electrical shorting and defects occur
Solution Approach 1:
The sidewall protection layer is formed as a preliminary step in the fabrication process. This additional step, while slightly increasing process complexity, prevents electrical shorting and defects, thereby significantly improving yield and overall manufacturing reliability.
Data Source
AI summary
A sidewall protection layer is formed on sidewall spacers of a dummy gate structure of a semiconductor device prior to etching an underlying fin structure to form a source/drain recess. The sidewall protection layer enables the profile of the source/drain recess to be precisely controlled so that etching into residual dummy gate material near the source/drain recess is minimized or prevented. The sidewall protection layer may be removed or retained in the semiconductor device after formation of the source/drain recess. The sidewall protection layer reduces the likelihood of the source/drain regions of the semiconductor device contacting the metal gate structures of the semiconductor device after the dummy gate structures are replaced with the metal gate structures. Thus, the sidewall protection layer reduces the likelihood of electrical shorting between the source/drain regions and the metal gate structures.