Dummy Gate Stack Oxide Layer for CMP Planarization

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Solution Overview

Problem

The chemical mechanical polishing (CMP) process in semiconductor manufacturing can cause damage to flash memory cells due to uneven removal amounts in different areas, leading to potential damage to the gate stack in the first region.

Innovation Solution

An oxide layer is formed on the exterior wall and top surface of the dummy gate stack, creating a concave bowl-shaped top surface for the dummy conductive layer, which compensates for uneven removal during the CMP process, protecting the gate stack from damage and allowing for increased polishing velocity and pressure without surface irregularities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a CMP process is performed on a planar dummy conductive layer, then the polishing process is simple and fast, but the gate stack in the first region suffers from uneven removal amounts and potential damage

Engineering Contradiction:

Improvepolishing velocityVSAvoiduniformity of removal amount

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The dummy conductive layer is designed with different top surface profiles in different regions: a concave bowl-shaped surface in the first region (over gate stacks) and a planar surface in the second region. This local variation in surface geometry compensates for the non-uniform polishing rates, allowing high polishing velocity while maintaining uniform removal amounts across different areas.

Inventive Principle:

Principle #3Local quality

2Area of stationary object

If the dummy gate stack width is reduced to minimize device size, then the overall device footprint decreases, but the protection capability against CMP damage to the gate stack is weakened

Engineering Contradiction:

Improvedevice footprintVSAvoidprotection capability against CMP damage

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The top surface of the dummy conductive layer in the first region is formed with a concave bowl-shaped curvature. This curved profile allows the polishing pad to maintain consistent contact and pressure distribution across the narrower dummy gate stack, providing adequate protection against CMP damage while enabling reduction of the dummy gate stack width and overall device footprint.

Inventive Principle:

Principle #14Spheroidality (Curvature)

3Productivity

If high polishing pressure is applied to increase polishing efficiency, then the polishing process is faster and more efficient, but the risk of damage to the gate stack increases

Engineering Contradiction:

Improvepolishing efficiencyVSAvoidCMP-induced damage risk

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The dummy conductive layer with concave bowl-shaped top surface is formed in advance before the CMP process. This pre-formed geometry serves as a protective profile that distributes polishing pressure uniformly during the CMP process, enabling the use of high polishing pressure for improved efficiency while the concave profile prevents concentration of stress that could damage the underlying gate stack.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents damage to the gate stack by ensuring a planar surface post-CMP, reduces the overall processing time, and allows for a reduction in the size of the semiconductor structure by minimizing the width of the dummy gate stack, while maintaining protection from CMP-induced damage.

Implementation Method 1

performing a chemical mechanical polishing (CMP) process on the dummy conductive layer

Methodology Applied

Scientific EffectChemical mechanical polishing:

Data Source

PatentUS9922832B1Manufacturing method of semiconductor structure

Publication Date: 2018.03.20 UNITED MICROELECTRONICS CORP

AI summary

A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region surrounding the first region; forming a gate stack and a dummy gate stack in the first region, wherein the dummy gate stack surrounds the gate stack; forming an oxide layer on an exterior wall and a top surface of the dummy gate stack; forming a dummy conductive layer on the gate stack, the dummy gate stack and the oxide layer, wherein the dummy conductive layer has a concave bowl-shaped top surface in the first region; and performing a chemical mechanical polishing (CMP) process on the dummy conductive layer.