Dummy Gate Stack Shielding for Parasitic Capacitance in CMOS Devices
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the difficulty in preventing parasitic capacitance among gate stacks due to reduced spacing, which affects device performance, especially in complementary metal-oxide-semiconductor (CMOS) technology as gate length and spacing decrease.
Innovation Solution
A method for fabricating semiconductor devices involves forming gate stacks with a dummy gate stack and inter-layer dielectric (ILD) layers, where the dummy gate stack is strategically placed between active gate stacks to reduce parasitic capacitance, and the ILD layers are used to manage the spacing and resistance between conductive gate materials, including transforming the gate electrode to increase resistance and using metal gates to replace poly-silicon gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gate length and spacing are decreased to scale down the semiconductor device, then device integration density is improved, but parasitic capacitance among gate stacks increases
Solution Approach 1:
A dummy gate stack is introduced as an intermediary structure between adjacent active gate stacks. This dummy gate stack acts as a shield that reduces the parasitic capacitance coupling between neighboring gate stacks, allowing the device to achieve higher integration density without suffering from excessive parasitic effects.
Solution Approach 2:
The resistance of the gate electrode is modified by transforming it into a metal gate structure with different electrical characteristics. This parameter change in resistance helps to reduce the parasitic capacitance effect and improve device performance at scaled dimensions.
2Reliability
If metal gate electrode layer is incorporated to replace poly-silicon gate, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The gate electrode is transformed into a metal gate structure before the final gate stack formation is completed. This preliminary action allows subsequent processing steps to be simplified, as the metal gate structure can be integrated more easily with the high-k dielectric layer and the dummy gate stack formation.
3Area of stationary object
If gate stacks are placed closer together to reduce spacing, then area utilization is improved, but parasitic capacitance increases affecting device performance
Solution Approach 1:
The dummy gate stack serves as an intermediary shielding structure that enables closer spacing between active gate stacks while maintaining acceptable parasitic capacitance levels. This allows improved area utilization without sacrificing device performance.
Data Source
AI summary
A semiconductor device includes an inter-layer dielectric (ILD) layer over a substrate; and a first gate feature in the ILD layer, the first gate feature comprising a first gate material and having a first resistance, wherein the first gate material comprises a first conductive material. The semiconductor device further includes a second gate feature in the ILD layer, the second gate feature comprising a second gate material and having a second resistance higher than the first resistance, wherein the second material comprises at least 50% by volume silicon oxide.