Dummy Gate Strain Inserts for Carrier Mobility
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Solution Overview
Problem
Conventional methods for enhancing carrier mobility in MOS transistors using SiGe inserts face challenges due to suboptimal strain distribution and mechanical support issues, particularly in fine geometry FETs, where the disposable gate structures may not align correctly with the isolation oxide, leading to reduced stress in the channel region.
Innovation Solution
The approach involves forming active and dummy gate structures with the same width, using sidewall spacers to create recesses for strain-inducing inserts like epitaxially grown SiGe or SiC, which extend between the active gate and dielectric isolation structure, ensuring a semiconductor portion remains between the insert and the isolation oxide, thereby enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe inserts are formed to abut oxide for isolation, then carrier mobility is enhanced through strain, but the SiGe-induced stress in the channel is reduced due to the soft oxide
Solution Approach 1:
A dummy gate structure is introduced as an intermediary element between the SiGe insert and the isolation oxide. The dummy gate provides a rigid support structure that allows the SiGe insert to maintain proper alignment and exert sufficient strain on the channel without directly contacting the soft oxide, thereby resolving the contradiction between enhancing carrier mobility and maintaining adequate stress
Solution Approach 2:
The dummy gate structure is created as a copy of the active gate structure, positioned adjacent to it. This copied structure serves the specific function of providing mechanical support for the SiGe insert alignment without performing the electrical function of the active gate, allowing the SiGe insert to achieve proper positioning and stress transmission
2Strength
If disposable gate structures are made wider than active gate structures to provide mechanical support, then wafer processing is improved, but the structures are mismatched in very fine geometry FETs
Solution Approach 1:
The dummy gate structure is designed with local quality - it has the same width as the active gate structure in the critical region where alignment with the isolation oxide is needed, while extending only as far as necessary to provide the required mechanical support. This localized matching of dimensions resolves the contradiction between providing adequate mechanical support and achieving precise alignment
3Reliability
If the offset from isolation oxide is optimized for SiGe inserts, then strain distribution is improved, but it may not equal the optimum gate electrode-drain/source offset
Solution Approach 1:
The gate structure system is segmented into two independent components: the active gate structure that determines the gate electrode-drain/source offset, and the dummy gate structure that determines the SiGe insert offset from the isolation oxide. This segmentation allows each component to be independently optimized for its specific function without compromising the other, resolving the contradiction between strain distribution optimization and offset alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases carrier mobility by maintaining a semiconductor portion for the strain-inducing inserts to nucleate on, providing increased strain and improved channel operation, particularly in edging FETs and fine geometry devices, thus enhancing the performance of PMOS and NMOS transistors.
Implementation Method 1
produce strain in the channel... create strain in the channel region... providing increased strain and improved channel operation
Implementation Method 2
epitaxially grown SiGe... epitaxially grown SiC... strain-inducing insert formed in the semiconductor substrate
Implementation Method 3
A first sidewall spacer disposed on a first sidewall of the active gate structure has a first sidewall spacer width... A second sidewall spacer disposed on a second sidewall of the dummy gate structure has a second sidewall spacer width
Implementation Method 4
Disposable gate structures provide beneficial mechanical support when performing chemical-mechanical polishing or other wafer processing
Implementation Method 5
A recess is formed in the semiconductor wafer extending from the first sidewall spacer to the second sidewall spacer
Data Source
AI summary
An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.