Dummy Gate High Voltage Transistor Drain Extension
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Solution Overview
Problem
Traditional methods for fabricating high voltage semiconductor transistor devices face challenges in achieving a sufficient voltage drop as transistor sizes decrease, making it impractical to lengthen the drain region, which affects the complexity and efficiency of the manufacturing process.
Innovation Solution
The introduction of a dummy gate structure, where a gate stack is formed over a portion of the substrate, separated from the device gate by a gap, allows for self-aligned formation of the drain region, reducing overlay requirements and enabling accurate control of the drain region's size and position, thereby increasing the resistance of the conductive path without increasing the device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drain region is lengthened to achieve sufficient voltage drop, then the voltage drop is improved, but the device size increases
Solution Approach 1:
The patent introduces a dummy gate structure that is physically separated from the main device gate by a gap. This segmentation allows the drain region to be extended under the dummy gate without proportionally increasing the overall device footprint, as the dummy gate area can be optimized independently to achieve the required voltage drop while maintaining compact device dimensions.
2Reliability
If the drain region is lengthened to achieve sufficient voltage drop, then the voltage drop is improved, but the manufacturing complexity increases
Solution Approach 1:
The dummy gate structure is formed in advance during the fabrication process, establishing the drain region boundaries and extent before subsequent processing steps. This preliminary action simplifies manufacturing by pre-defining the extended drain region geometry, eliminating the need for complex alignment and patterning operations that would otherwise be required to achieve the same voltage drop.
3Productivity
If the device size is reduced, then the transistor density is improved, but the voltage drop decreases
Solution Approach 1:
The patent extends the drain region in a spatial dimension by utilizing the area under the dummy gate structure. This dimensional approach allows the effective drain length to increase without proportionally increasing the device's lateral footprint, thereby maintaining high transistor density while achieving the necessary voltage drop for high-voltage operation.
Data Source
AI summary
The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.