Dummy Gate Bottom-Up Deposition for FinFET Void Reduction
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, issues such as fin bending, seam formation, and voids in dummy gates arise, leading to decreased device yield and increased failure rates.
Innovation Solution
A bottom-up deposition process is employed to form improved dummy gates, where a dummy gate seed layer is deposited over fins, reflowed into trenches, etched using a halogen-gas etch, and then selectively deposited with additional material at a higher rate than on the dummy dielectric layer, followed by planarization to form the dummy gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional top-down deposition process is used to form dummy gates, then the process is simpler and faster, but fin bending and seam formation occur leading to decreased device yield
Solution Approach 1:
The patent inverts the conventional top-down deposition approach by using bottom-up deposition. Instead of depositing material from the top surface downward onto the fins, the deposition starts from the bottom of the fins and progresses upward, filling trenches from below. This inversion eliminates the formation of seams and voids that occur in top-down processes, as material is deposited conformally from the base upward, ensuring complete coverage without trapping air or creating interface defects.
Solution Approach 2:
The patent transitions from a two-dimensional top-down surface deposition to a three-dimensional bottom-up volumetric filling process. By depositing material from the bottom of the trenches upward along the fin sidewalls, the process utilizes the vertical dimension more effectively, ensuring uniform coverage and eliminating the seam formation that occurs when material is deposited from above. This dimensional change allows for better control of material distribution and eliminates the harmful effects of top-down deposition.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but fin bending and void formation increase leading to higher failure rates
Solution Approach 1:
The patent applies preliminary action by performing bottom-up deposition that completely fills trenches and eliminates voids before subsequent processing steps. By ensuring complete material coverage and eliminating potential defect sites (voids and seams) in advance, the process prevents fin bending and structural failures that would otherwise occur during later manufacturing steps. This preliminary defect elimination maintains high device yield even as feature sizes are reduced to increase integration density.
3Reliability
If dummy gates are formed using conventional processes, then the manufacturing process is faster, but seams and voids form in the dummy gates decreasing device reliability
Solution Approach 1:
The patent changes the deposition parameters by switching from conventional top-down deposition to bottom-up deposition. This parameter change fundamentally alters the material deposition mechanism, ensuring that material is deposited conformally from the bottom upward, which eliminates seam and void formation. Although the process may take slightly longer due to the bottom-up approach, the significant improvement in device yield and elimination of rework compensates for the additional time, resulting in net productivity improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process prevents fin bending and reduces the formation of seams or voids in the dummy gates, thereby improving device yield and reducing failure rates.
Implementation Method 1
The dummy gate seed layer may be reflowed from above the fins into trenches adjacent the fins
Implementation Method 2
The dummy gate seed layer may be etched by a halogen-gas etch
Implementation Method 3
An additional deposition process may be performed over the dummy gate seed layer and the dummy dielectric layer
Data Source
AI summary
A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.