Dummy Gate Width Control via Trimmed ONO Hard Mask
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Solution Overview
Problem
In the gate-last process for MOSFET manufacturing, the critical dimension and profile of the dummy gate cannot be accurately controlled at the 22 nm node and beyond, leading to degraded gate Line Edge Roughness, device performance, and reliability.
Innovation Solution
A method involving the deposition of a gate oxide layer, bottom-layer amorphous silicon, an oxide-nitride-oxide structured hard mask, and a top-layer amorphous silicon, followed by trimming and etching of the hard mask layers to achieve a width of 22 nm or less, ensuring precise control over the dummy gate dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate-last process is used, then manufacturing simplicity is maintained, but manufacturing precision of dummy gate critical dimension deteriorates
Solution Approach 1:
The dummy gate structure is segmented into multiple layers: gate oxide layer, bottom amorphous silicon layer, ONO hard mask layer, and top amorphous silicon layer. Each layer is deposited and etched separately, allowing precise control of the critical dimension through the trimmed hard mask layer while maintaining systematic process management
Solution Approach 2:
The hard mask layer is trimmed to the target width (≤22 nm) before the actual etching of the amorphous silicon layers. This preliminary action ensures that the etching process starts with a precisely defined mask, enabling accurate critical dimension control of the dummy gate structure
2Manufacturing precision
If dummy gate critical dimension is not accurately controlled, then manufacturing simplicity is maintained, but gate Line Edge Roughness deteriorates
Solution Approach 1:
The hard mask layer is selectively trimmed to the target width in the critical region where the dummy gate will be formed. This local quality enhancement ensures that the mask has precise dimensions (≤22 nm) exactly where needed, which directly translates to improved line edge roughness and gate profile accuracy
Solution Approach 2:
The ONO structured hard mask layer serves as an intermediary between the lithography pattern and the amorphous silicon layers. The trimmed hard mask provides a stable, precisely-defined template that mediates the transfer of the desired critical dimension to the dummy gate structure, ensuring accurate profile control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for accurate control of the dummy gate's critical dimension and profile, thereby improving gate Line Edge Roughness and ensuring device performance and reliability at the 22 nm node and beyond.
Implementation Method 1
growing a gate oxide layer on the semiconductor substrate
Implementation Method 2
depositing bottom-layer amorphous silicon (α-Si) on the gate oxide layer
Implementation Method 3
depositing an oxide-nitride-oxide (ONO) structured hard mask on the bottom-layer α-Si
Data Source
AI summary
A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.