Stacked Semiconductor Package Dummy Grid for Warpage Relief
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Solution Overview
Problem
The increasing size of high bandwidth memory semiconductor packages due to high specification requirements leads to stress issues from coefficient of thermal expansion differences and increased process complexity, resulting in degraded yield and reliability.
Innovation Solution
A semiconductor package design that includes a dummy pattern on the silicon substrate surrounding chip pads, using either a metal film or polymer film, to reduce warpage and improve connection reliability between dies, which are electrically connected through vias and terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of high bandwidth memory semiconductor package is increased to meet high specification requirements, then the memory capacity and performance are improved, but stress due to coefficient of thermal expansion difference increases and process difficulty increases
Solution Approach 1:
The semiconductor package is divided into multiple dies (first die and second die) that are stacked vertically and connected through connection terminals. This segmentation allows the package to achieve high memory capacity without proportionally increasing the lateral footprint, thereby reducing thermal expansion stress and simplifying the manufacturing process compared to a single large die architecture.
2Quantity of substance
If the size of high bandwidth memory semiconductor package is increased to meet high specification requirements, then the memory capacity and performance are improved, but yield is degraded
Solution Approach 1:
Dividing the package into multiple smaller dies reduces the area of each individual die, which decreases the probability of defects and improves yield. The segmented architecture allows for better process control and higher manufacturing yield while achieving the required total memory capacity through vertical stacking.
Solution Approach 2:
The invention changes the architectural parameters from a single large die to multiple smaller stacked dies. This parameter change optimizes the balance between memory capacity and manufacturing yield by reducing the critical area for defects while maintaining the required total storage capacity.
3Quantity of substance
If the size of high bandwidth memory semiconductor package is increased to meet high specification requirements, then the memory capacity and performance are improved, but stress due to coefficient of thermal expansion difference increases
Solution Approach 1:
Segmenting the package into multiple smaller dies reduces the overall lateral dimensions and the area subject to thermal expansion stress. The vertical stacking architecture minimizes the lateral footprint, thereby reducing the cumulative thermal expansion stress compared to a single large die configuration with equivalent memory capacity.
4Stability of the object's composition
If dummy pattern is added to the die structure to reduce warpage, then warpage and stress are reduced, but device complexity increases
Solution Approach 1:
The dummy pattern is strategically placed in specific regions of the die (such as around connection terminals or in areas prone to warpage) rather than uniformly across the entire die. This localized approach provides effective warpage control while minimizing the additional structure and complexity introduced by the dummy pattern.
Data Source
AI summary
Provided is a semiconductor package. The semiconductor package may comprise a first die, a second die on the first die, and connection terminals, the first die comprises: a first silicon substrate that has a lower side and an upper side opposite to the lower side, first through vias, first chip pads, and a first dummy pattern on the upper side of the first silicon substrate, the first dummy pattern having a grid shape from a plan view and at least partially surrounding each of the first chip pads, the second die comprises: a second silicon substrate that has a lower side and an upper side opposite to the lower side, and second through vias, wherein the connection terminals and the first chip pads are in contact with each other and are electrically connected, respectively, and wherein the first dummy pattern includes a metal film or a polymer film.