3D NAND Dummy Memory Hole Defect Detection via Shared Bit Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Detecting defects in dummy memory holes of 3D NAND memory structures is challenging due to their electrical floating nature and lack of associated circuitry, which can impair the proper operation of the memory system.
Innovation Solution
A stress test is applied to dummy memory holes by connecting dummy bit lines together and using a stress voltage to detect defects, with the system sensing the dummy bit lines for electrical shorts or other defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy memory holes are not monitored, then device complexity is reduced, but reliability deteriorates due to undetected electrical shorts
Solution Approach 1:
The dummy bit lines are connected together to form a common node that serves multiple dummy memory holes, allowing a single sensing operation to detect defects across multiple dummy holes simultaneously. This multi-functional approach enables defect monitoring without requiring separate circuitry for each dummy hole, thus improving reliability while minimizing added complexity.
Solution Approach 2:
The existing bit line infrastructure is utilized for defect detection in dummy memory holes. By connecting dummy bit lines together and using the same sensing circuitry that operates on real memory holes, the system leverages its own existing resources to perform self-diagnosis, eliminating the need for separate monitoring circuitry.
2Ease of manufacture
If dummy memory holes are electrically floating, then manufacturing is simplified, but measurement precision deteriorates for defect detection
Solution Approach 1:
By connecting all dummy bit lines together, the patent creates an equipotential network where all dummy memory holes share the same electrical reference. This allows the sensing circuit to detect leakage currents from any dummy hole against a common reference potential, enabling accurate defect detection while maintaining the simple floating structure during manufacturing.
Solution Approach 2:
The common bit line connection acts as an intermediary that translates the electrical floating state of individual dummy memory holes into a measurable collective signal. By summing the electrical states of all dummy holes through the shared bit line, the system can detect defects without requiring each dummy hole to have individual electrical connections.
3Measurement precision
If stress voltage is applied to detect defects, then measurement precision improves, but harmful factors increase due to potential damage
Solution Approach 1:
The patent applies stress voltages selectively only to dummy memory holes during defect detection operations, not during normal memory operations. By limiting stress application to specific detection phases and using controlled voltage levels, the system achieves high detection sensitivity while minimizing cumulative electrical stress damage to the memory structure.
Solution Approach 2:
Defect detection using stress voltage is performed periodically or at specific stages (such as during manufacturing testing or at intervals during operation) rather than continuously. This periodic application allows the memory to operate normally between tests while still maintaining high defect detection capability when stress is applied, balancing measurement precision with harm reduction.
Data Source
AI summary
Technology for detection of defects in dummy memory holes in a 3D NAND memory structure. Dummy bit lines connected to dummy memory holes are used to detect defects associated with the dummy memory holes. A system may perform a stress test in which a stress voltage is applied to one or more word lines while another voltage (e.g., 0V) is applied to the dummy bit lines. The system may detect defects associated with the dummy memory holes by sensing the dummy bit lines. The dummy bit lines may be electrically connected with each other which reduces the amount of circuitry for providing a voltage to the dummy bit lines and/or sensing the dummy bit lines.