Thin-Film Resistor Structure Using Dummy Layers Against CMP Erosion
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Solution Overview
Problem
Conventional thin film resistors in semiconductor integrated circuits face issues such as CMP dishing and erosion due to the long extension of polysilicon line structures, leading to over-polishing and over-etching, which are not entirely satisfactory.
Innovation Solution
A thin film resistor is formed with a metal thin film disposed above a semiconductor substrate and a dummy layer, where recessed regions in the dummy layer are filled with polishing resistance material to minimize dishing and erosion effects during the CMP process, allowing for concurrent formation with MOSFETs and compatibility with CMOS fabrication technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a CMP process is performed on a substantially long polysilicon line structure to form the metal gate and contacts of the thin film resistor, then the thin film resistor can be formed concurrently with the metal gate, but CMP dishing and erosion effects occur leading to over-polishing and over-etching
Solution Approach 1:
The patent applies local quality by introducing a dummy layer with specific local structures (recessed regions filled with polishing resistance material) at predetermined positions along the polysilicon line structure. This creates non-uniform local properties that compensate for the inherent polishing non-uniformity across the long line structure, ensuring uniform polishing depth and preventing dishing and erosion effects while maintaining concurrent formation capability.
2Reliability
If the polysilicon line structure is made substantially long to overlay the metal thin film, then the thin film resistor can be formed with proper contacts, but dishing and erosion effects are exacerbated
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the dummy layer with recessed regions filled with polishing resistance material at predetermined positions before the CMP process. This preliminary structural arrangement creates counterbalancing effects that prevent the harmful dishing and erosion effects from occurring during polishing, thereby protecting the polysilicon line structure and contact regions while maintaining the necessary long extension for reliable contact formation.
Data Source
AI summary
A semiconductor device includes: a metal thin film disposed on a semiconductor substrate; and first and second contact structures disposed on the metal thin film, wherein the first and second contact structures are laterally spaced from each other by a dummy layer that comprises at least one polishing resistance material.