Variable Width Dummy Line Placement for Parasitic Capacitance Reduction
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Solution Overview
Problem
In semiconductor manufacturing, the placement of dummy lines in close proximity to signal lines leads to increased parasitic capacitance and signal transmission delays due to defects causing short-circuits, which are not effectively addressed by existing methods that focus on pattern density and capacitance coupling, resulting in malfunction and high mask production costs.
Innovation Solution
A design method where dummy lines are placed in a 'floating state' with varying widths and divided lengths based on distance from signal lines, using a computer program to manage pattern density and minimize parasitic capacitance by dividing dummy lines near signal lines to prevent short-circuit effects and reduce mask data complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large dummy line is placed in close proximity to a signal line to equalize pattern density, then the surface of the line layer is equalized and mask data amount is reduced, but parasitic capacitance of lines increases causing larger signal transmission delay
Solution Approach 1:
The patent applies local quality by making the dummy line width variable rather than uniform. The dummy line has a first width in regions away from signal lines and a second width (narrower than the first) in regions close to signal lines. This local variation in dummy line width allows the pattern density to be equalized in the overall region while minimizing the parasitic capacitance in the critical area near signal lines, thus resolving the contradiction between pattern density equalization and signal transmission delay.
2Quantity of substance
If dummy lines are placed close to signal lines to equalize pattern density, then mask data amount is reduced, but the number of patterns increases due to finer design rules requiring more blocks
Solution Approach 1:
The patent changes the parameter of dummy line width based on the distance from signal lines. By using a narrower width for dummy lines close to signal lines and a wider width for dummy lines farther away, the design reduces the total number of separate pattern blocks needed. This parameter variation allows fewer, larger dummy line structures to achieve the same pattern density equalization that would otherwise require many small blocks, thus reducing mask data amount while avoiding the complexity increase from finer design rules.
3Productivity
If the distance between lines is shortened to reduce area, then productivity is improved, but capacitance coupling occurs and parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by differentiating the dummy line width based on spatial proximity to signal lines. In regions where the distance to signal lines is small, the dummy line uses a narrower width to minimize capacitance coupling. In regions farther from signal lines, the dummy line uses a wider width to maximize area utilization. This localized adjustment allows the overall area to be reduced while controlling parasitic capacitance in the critical proximity regions where it would otherwise be problematic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and signal delays, enhances semiconductor apparatus reliability, and decreases the time and cost associated with optical proximity correction and mask production by minimizing the number of patterns and data amount.
Implementation Method 1
capacitance coupling occurs between lines and parasitic capacitance increases accordingly
Data Source
AI summary
A design method places a dummy line in floating state in a line layer of a semiconductor apparatus by using a computer. The method includes a first step of reading layout data and placing a dummy line with a longitudinal side lying in parallel with a signal line in an area where a pattern density of the signal line in a prescribed area is equal to or lower than a density lower limit, and a second step of dividing a dummy line placed in an area where a distance from the signal line is equal to or shorter than a dummy dividing distance.