Dummy Lines with Variable Widths for Transistor Shielding
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Solution Overview
Problem
Transistors in stacked memory arrays face challenges due to electric fields produced during fabrication, leading to changes in source-drain breakdown voltage, drain-to-source current, and saturation current, which affect their performance and reliability.
Innovation Solution
Incorporating dummy lines with different collective widths between transistors to mitigate the impact of electric fields, these dummy lines are strategically placed to reduce the likelihood of charge trapping in dielectric materials and minimize the induction of negative charges on source/drain regions, thereby maintaining optimal transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are located under stacked memory arrays to save space, then device integration density is improved, but electric fields during fabrication cause changes in source-drain breakdown voltage and transistor characteristics
Solution Approach 1:
Conductive dummy lines are introduced as intermediary elements between the memory array and the transistor. These dummy lines act as shields that intercept and redirect electric fields during fabrication, preventing direct interaction between the electric fields and the transistor channels, thus protecting transistor characteristics while maintaining high integration density
Solution Approach 2:
The harmful electric fields generated during memory array fabrication are converted into a beneficial shielding effect by strategically placing conductive dummy lines. The same electric fields that would damage transistors are instead channeled through the dummy lines, which are positioned to absorb or redirect these fields away from sensitive transistor regions
2Reliability
If dummy lines are added to shield transistors from electric fields, then transistor reliability is improved, but device complexity increases
Solution Approach 1:
The complexity issue is resolved by varying parameters of the dummy lines rather than adding complex structures. The collective width of dummy lines is adjusted based on their position relative to transistors, with wider dummy lines closer to transistors providing stronger shielding. This parameter-based approach achieves effective protection while maintaining manufacturing simplicity
Solution Approach 2:
Different regions of the device receive different levels of shielding based on their specific needs. Dummy lines are strategically placed only where electric field exposure is most problematic, and their widths are locally optimized. This localized approach provides targeted protection without uniformly increasing complexity across the entire device
3Reliability
If dummy lines with larger collective width are used closer to transistors, then shielding effectiveness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The shielding function is segmented into multiple dummy lines rather than using a single large structure. Each dummy line can be manufactured within standard precision tolerances, but collectively they provide the equivalent shielding of a much wider structure. This segmentation allows effective shielding while maintaining compatibility with existing manufacturing capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of dummy lines helps in maintaining the source-drain breakdown voltage and saturation current, reducing leakage, and enhancing the overall performance and reliability of transistors in stacked memory arrays by shielding the dielectric from electric fields and preventing charge trapping.
Implementation Method 1
electric fields that might be produced during fabrication processes in the memory array above the transistors
Implementation Method 2
reducing the likelihood of charge trapping in dielectric materials
Data Source
AI summary
In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.