Dummy Memory Cell Capacitance Matching for ReRAM Read Speed
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Solution Overview
Problem
In high-speed read operations of nonvolatile memory devices like ReRAM, a mismatch in drive load capacitance between the bit line and the reference bit line occurs due to the inability to form dummy memory cells, leading to longer read times and increased current consumption.
Innovation Solution
The configuration includes a dummy memory cell with both ends of the resistance change element short-circuited through the reference data line, allowing the drive load capacitances of via contacts and interconnects to be reflected on the reference data line, matching the drive load capacitance with the memory cell's data line, or a configuration where the dummy memory cell has no resistance change element, with one end of the cell transistor connected to the reference data line, reflecting the drive load capacitances of via contacts and interconnects on the reference data line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dummy memory cells are connected to the reference bit line to match load resistance, then load resistance matching is improved, but drive load capacitance mismatch persists and device complexity increases
Solution Approach 1:
The invention extracts the resistance change element from the dummy memory cell configuration, connecting only the cell transistor to the reference bit line. This removes the problematic capacitance contribution from the resistance change element while maintaining the load resistance matching function, thereby resolving the capacitance mismatch issue.
Solution Approach 2:
The dummy memory cell is segmented into only the cell transistor portion, separating it from the resistance change element. This segmentation allows the reference bit line to match load resistance while avoiding the capacitance mismatch that would result from including the resistance change element.
2Speed
If read operation is performed in transient state before current saturation, then read speed is improved, but read precision deteriorates due to capacitance mismatch
Solution Approach 1:
The invention creates equipotential conditions by ensuring both the bit line and reference bit line have matched drive load capacitances. This allows simultaneous charging of both lines during read operation, maintaining equal potential rise and enabling accurate current comparison in the transient state without precision loss.
3Measurement precision
If wiring width and length of bit line and reference bit line are made the same, then load resistance matching is improved, but drive load capacitance mismatch remains due to different number of connected cells
Solution Approach 1:
The invention creates a copy of the memory cell structure (cell transistor) on the reference bit line without copying the resistance change element. This copying approach matches the load resistance characteristics while controlling the capacitance to match the bit line's drive load capacitance.
Data Source
AI summary
A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.