Dummy Memory Cell Programming for Select Gate Vth Downshift
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Solution Overview
Problem
In semiconductor memory devices, particularly in 3D NAND structures, the threshold voltage (Vth) of select gate transistors decreases over time due to hole migration from dummy memory cells to select gate transistors, leading to charge loss and uncorrectable errors.
Innovation Solution
Implementing weak programming of dummy memory cells during erase operations, where a brief program pulse is applied after an erase bias and before an erase-verify test, with the magnitude of the pulse increasing in successive erase loops and as a function of program-erase cycles, to minimize hole migration and maintain Vth within a specified range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy memory cells are left unprogrammed during erase operations, then erase operation simplicity is maintained, but hole migration to select gate transistors causes threshold voltage downshift and charge loss
Solution Approach 1:
The patent applies a preliminary program pulse to dummy memory cells during erase operations, before the erase-verify test. This preliminary action prepares the dummy cells by injecting electrons into their charge-trapping layers, which prevents subsequent hole migration to select gate transistors and maintains threshold voltage stability throughout the erase operation and subsequent cycles.
Solution Approach 2:
The patent dynamically adjusts the program pulse magnitude based on the number of program-erase cycles performed. As the cycle count increases, the program pulse magnitude is increased to compensate for accumulated charge loss in select gate transistors, thereby maintaining threshold voltage within the specified range throughout the device lifetime.
2Reliability
If program pulse magnitude is increased in successive erase loops, then threshold voltage downshift is reduced, but energy consumption increases
Solution Approach 1:
The patent implements a dynamic program pulse magnitude that adapts based on the number of program-erase cycles performed. The pulse magnitude starts at a baseline level and increases progressively as cycle count increases, allowing the system to optimize between energy consumption and charge retention requirements at different stages of device operation.
3Reliability
If weak programming is applied to dummy memory cells, then hole migration is minimized, but additional operation steps are required
Solution Approach 1:
The patent merges the weak programming of dummy memory cells with the existing erase operation sequence. The program pulse is applied during the erase operation itself, specifically after the erase bias is applied and before the erase-verify test, thereby combining two functions (dummy cell preparation and erase operation) into a single integrated process without requiring separate operation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces Vth downshift in select gate transistors, minimizing charge loss and uncorrectable errors, thereby enhancing the reliability and longevity of memory devices.
Implementation Method 1
circuitry configured to selectively inject electrons into portions of the channels within the dummy memory cells in the erase loop
Implementation Method 2
circuitry configured to inject holes into the channels in an erase loop of an erase operation
Data Source
AI summary
Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.