Dummy Memory Cell Thickness for Recess Defect Prevention
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Solution Overview
Problem
Semiconductor devices, such as PRAM and RRAM, face challenges in reducing recess defects in data storage patterns during the planarization process, which affects high integration and cost efficiency.
Innovation Solution
The semiconductor device incorporates a structure with dummy memory cells and main memory cells, where the dummy cells are connected to or float from active regions, and have a different thickness than main memory cells, preventing recess defects by maintaining a consistent structure during the polishing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of dummy memory cells is increased to prevent recess defects, then recess defect prevention is improved, but device complexity and integration density deteriorate
Solution Approach 1:
The patent applies local quality by creating different thickness levels for dummy memory cells versus main memory cells. Specifically, dummy memory cells are formed with a first thickness while main memory cells have a second thickness greater than the first. This localized structural differentiation allows the dummy cells to effectively prevent recess defects during CMP without requiring increased quantity, thereby maintaining high integration density while improving reliability.
2Reliability
If a novel slurry material is developed to prevent recess defects, then recess defect prevention is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies parameter changes by modifying the physical structure of dummy memory cells (thickness parameter) rather than changing the chemical composition of the slurry material. By forming dummy cells with a first thickness and main memory cells with a second thickness, the invention changes the geometric parameters of the structure to achieve uniform CMP polishing, thereby preventing recess defects using conventional slurry materials and avoiding additional manufacturing costs.
3Ease of manufacture
If dummy memory cells are made with the same structure as main memory cells, then manufacturing simplicity is improved, but recess defect prevention deteriorates
Solution Approach 1:
The patent applies local quality by creating distinct thickness levels for dummy memory cells versus main memory cells. Dummy memory cells are formed with a first thickness while main memory cells have a second thickness greater than the first. This localized structural differentiation allows the dummy cells to effectively prevent recess defects during CMP without requiring increased quantity, thereby maintaining high integration density while improving reliability.
Data Source
AI summary
A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.