Dummy Memory Structures for CMP Density Balancing
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Solution Overview
Problem
The varying area densities of conductive structures in semiconductor devices during planarization operations lead to loading effects such as dishing, erosion, and uneven feature thickness, resulting in reduced process control and yield, particularly in memory cell arrays and peripheral circuits.
Innovation Solution
Incorporation of dummy memory cells in the peripheral circuit region with adjusted conductor densities to mimic the memory cells, balancing area densities and mitigating loading effects during planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planarization operations are performed on semiconductor devices with varying area densities of conductive structures, then the manufacturing process can be completed, but loading effects such as dishing, erosion, and uneven feature thickness occur, reducing process control and yield
Solution Approach 1:
The patent applies local quality by introducing dummy memory structures specifically in peripheral circuit regions where conductor area density differs from memory cell array regions. This creates locally adjusted area densities in specific regions (peripheral circuits) without changing the overall device structure, thereby balancing the CMP loading effects across different regions of the semiconductor device.
Solution Approach 2:
The patent changes the physical parameter of conductor area density by adding dummy memory structures with conductive elements in peripheral circuit regions. This modifies the local area density parameter to match that of memory cell array regions, thereby equalizing the material removal rate during CMP and eliminating loading effects.
2Manufacturing precision
If dummy memory structures are added to balance area densities, then loading effects are reduced and yield is enhanced, but device complexity increases
Solution Approach 1:
The patent uses copying by creating dummy memory structures that replicate the conductive element patterns of actual memory cells. These dummy structures are copies of the functional memory cell conductors, placed in peripheral circuit regions to mimic the area density characteristics of memory cell arrays, thereby simplifying the solution compared to designing entirely new compensation structures.
Solution Approach 2:
The dummy memory structures serve multiple functions: they balance the area density for CMP process control, provide etch loading compensation, and maintain pattern density uniformity. By making the dummy structures multi-functional, the patent reduces the need for separate compensation mechanisms, thereby managing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The inclusion of dummy memory cells helps in controlling relative metal area densities, reducing manufacturing defects, and enhancing yield by minimizing variations in material removal during chemical-mechanical polishing.
Implementation Method 1
minimizing variations in material removal during chemical-mechanical polishing
Data Source
AI summary
A semiconductor device includes memory structures in wiring layers in a first region of a substrate, the memory structures including storage elements in the wiring layers, a peripheral circuit in a second region of the substrate, and dummy memory structures in the wiring layers in the second region and vertically overlapping the peripheral circuit.