Dummy Metal Density Gradient for High Frequency Wiring
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Solution Overview
Problem
The presence of dummy metals under high frequency wirings in semiconductor devices increases parasitic capacitance, degrading the characteristics of inductors and transformers, and can lead to erosion and dishing during the CMP process, especially when their density varies.
Innovation Solution
A semiconductor device configuration with dummy metals dispersed in two regions: a high frequency wiring vicinity region and an external region, where the average interval between dummy metals in the vicinity region is wider than in the external region, reducing the number of dummy metals near the high frequency wiring and minimizing parasitic capacitance while preventing erosion and dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy metals are disposed densely to prevent erosion and dishing in CMP process, then manufacturing precision is improved, but parasitic capacitance increases degrading high frequency wiring characteristics
Solution Approach 1:
The patent applies local quality by differentiating the density of dummy metals in different spatial regions. Specifically, the dummy metals are disposed with lower density in the first region (under the high frequency wiring) and higher density in the second region (outside the high frequency wiring). This local differentiation allows the patent to prevent erosion and dishing in the CMP process while minimizing parasitic capacitance effects on the high frequency wiring.
2Ease of manufacture
If dummy metals are placed between high frequency wiring and semiconductor substrate, then ease of manufacture is improved, but device performance deteriorates due to increased capacitance
Solution Approach 1:
The patent segments the dummy metal distribution into two distinct regions: a first region under the high frequency wiring with lower dummy metal density, and a second region outside the high frequency wiring with higher dummy metal density. This segmentation allows the patent to maintain CMP process stability through adequate dummy metal coverage while reducing parasitic capacitance in the critical area under the high frequency wiring, thereby preserving inductor and transformer characteristics.
3Object-affected harmful factors
If dummy metals are disposed with wide intervals to reduce parasitic capacitance, then high frequency wiring characteristics are maintained, but erosion and dishing cannot be prevented effectively
Solution Approach 1:
The patent implements local quality by establishing different dummy metal densities in different regions. In the first region under the high frequency wiring, dummy metals are spaced wider apart to minimize parasitic capacitance. In the second region outside the high frequency wiring, dummy metals are disposed more densely to prevent erosion and dishing during CMP. This local differentiation resolves the contradiction between reducing parasitic capacitance and preventing manufacturing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses parasitic capacitance, maintains the characteristics of high frequency wirings, and stabilizes the manufacturing process by reducing the influence of surrounding dummy metals, thereby improving the semiconductor device's performance and manufacturing stability.
Implementation Method 1
the capacitance between the semiconductor substrate and the high frequency wiring increases in accordance with the thickness of the dummy metals
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first wiring layer including a plurality of first dummy metals provided inside an inductor wiring, a plurality of second dummy metals provided outside the inductor wiring, and a plurality of third dummy metals provided to overlap the inductor wiring in a plan view, and a second wiring layer provided between the semiconductor substrate and the first wiring layer. The second wiring layer includes the inductor wiring formed in the second wiring layer, a first region surrounding the inductor wiring which includes a plurality of fourth dummy metals, and a second region surrounding the first region which includes a plurality of fifth dummy metals. A density of the fourth dummy metals is lower than a density of the fifth dummy metals.